DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-18, 10-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Montijo, US PGPub 2017/0248634, hereafter “Montijo,” in view of Bartlett, EP 2293088 A2, hereafter “Bartlett.”
With respect to claim 1, Montijo teaches a method for using a data buffer for storing acquisition data, the method comprising:
initially storing acquisition data obtained from an oscilloscope in a data buffer (pars. 22-23, memory device is configured to operate as a circular buffer), the data buffer being controllable to operate in a segmented memory mode and a qualified store memory mode (par. 23, qualified store algorithm and par. 3, segmented memory mode):
wherein initially storing the acquisition data in the data buffer in the SRAM includes:
during an initial phase and prior to an end condition being met, iteratively providing a write pointer indicating one of a first set of memory locations of a first memory segment of the data buffer, wherein iteratively providing the write pointer includes updating the write pointer to a next memory location of the first set of memory locations in a circular manner after acquisition data from a data source is stored in a current memory location (par. 24 and fig. 2, in the Store Pre-Qual state, the circular buffer is continuously written and rewritten with N digital samples until the qualification signal becomes valid (the end condition of the claim). This is also illustrated in fig. 4, where Location 0 through Location N-1 are iteratively written before circling back to Location 0); and
in response to the end condition being met, changing the write pointer to indicate one of a second set of memory locations of a second memory segment of the data buffer (par. 25 and fig. 2, after the qualification signal becomes invalid (the end condition), the device enters the Store Post-Qual state, where data is written linearly into locations in a third portion of the memory device 114 (second segment of the data buffer). This is illustrated in fig. 4, as locations N+X+1 through 2N+X+M-1); and
Montijo fails to teach that the data buffer is implemented in SRAM, and transferring the acquisition data from the data buffer in the SRAM to a DRAM.
Bartlett teaches:
initially storing acquisition data from an oscilloscope in a data buffer implemented in a static random access memory (SRAM) (pars. 33-34, the acquisition memory storing data from the oscilloscope, and par. 42, the acquisition memory may be SRAM);
in response to the end condition being met, transferring the acquisition data from the data buffer in the SRAM to a dynamic random access memory (DRAM) (par. 82, the memory storing trigger events T associated with previously acquired data record, the data record coming from the acquisition memory as described in par. 47, and par. 42, the memory device may be DRAM).
It would have been obvious to one of ordinary skill in the art, having the teachings of Montijo and Bartlett before him before the earliest effective filing date, to modify the memory access method of Montijo with the memory access method of Bartlett, as it would be obvious to try. Bartlett lists the common types of memory used in a computer system, such as SRAM, DRAM, EPROM, EEPROM and flash memory and in addition, Bartlett discusses the problem of increasing the size of data records due to the trigger events, and thus affecting the performance of the systems (.e., “slow down”; see page 2, col. 2, lines 1-2) utilizing oscilloscopes . One of ordinary skill in the art would have been motivated to select from one of these common types of memories, as there are a limited number of common options that would be obvious to try. When there is a design need for market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp (KSR, 82 USPQ2d at 1397). As discussed in Bartlett, pars. 2-5, modern oscilloscopes require more memory than older oscilloscopes, and one of ordinary skill in the art having the teachings of Bartlett before him would choose from one of the listed memory options to meet the memory requirements of the oscilloscope.
With respect to claim 2, Montijo teaches the method of claim 1 wherein the data buffer is operating in the segmented memory mode and the first memory segment and the second memory segment are static in size (par. 41 and fig. 4, the first memory portion is the first memory segment, and the third memory portion is the second memory segment. Par. 41 discloses that the size values N and M may be factory settings, and thus are static values. Par. 3 discloses that this may be referred to as a “segmented memory mode”).
With respect to claim 3, Montijo teaches the method of claim 1 wherein the data buffer is operating in the segmented memory mode and while the data buffer is operating in the segmented memory mode, the method further comprising:
in response to or concurrently with changing the write pointer to indicate one of the second set of memory locations, changing a read pointer to indicate a first memory location of the first set of memory addresses; and until a last memory address of the first set of memory addresses is read, iteratively updating the read pointer to a next memory address of the first set of memory addresses after the acquisition data is read from the current memory address indicated by the read pointer (par. 27, the samples are read out of the memory device , including the N samples of pre-qualification data. Given that the pre-qualification samples, qualification samples and post-qualification samples are read out, this occurs after changing the write pointer to the second set of memory locations).
With respect to claim 4, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the method of claim 1 wherein the data buffer is operating in the qualified store memory mode (par. 23, qualified store algorithm) and the first memory segment and the second memory segment are dynamic in size (par. 23, the sizes are programmable by a user, and thus are dynamic in size).
With respect to claim 5, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the method of claim 1 wherein the data buffer is operating in the qualified store memory mode, the first memory segment includes the first set of memory locations and a third set of memory locations, the first set of memory locations include a static number of memory locations (Pars. 24-25, the first memory portion corresponds to the first set of memory locations, the second memory portion corresponds to the third set of memory locations. Par. 41 discloses that the size of the first set of memory locations, N, may be a factory setting, and thus is a static value.).
With respect to claim 6, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the method of claim 5 wherein the third set of memory locations is dynamic and based on the amount of data received after a qualifier signal is detected or after the qualifier signal is asserted (par. 25, in the Store Qual state, data is written into the second memory portion/third set of memory locations while the qualifier signal is asserted).
With respect to claim 7, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the method of claim 5 wherein the data buffer is operating in the qualified store memory mode and while the data buffer is operating in the qualified store memory mode, the method further comprising:
after the initial phase and prior to the end condition being met:
detecting a qualifier signal (par. 24, Qual becomes valid);
after detecting the qualifier signal, changing the write pointer to indicate one of the third set of memory locations (pars. 24-25, data begins writing to the second memory portion); and
prior to an end condition being met, iteratively providing the write pointer indicating one of a first set of memory locations of a first memory segment of the data buffer, wherein iteratively providing the write pointer includes updating the write pointer to a next memory location of the third set of memory locations in a linear manner after acquisition data from the data source is stored in a current memory location (pars. 24-25, data is written to the second memory portion linearly until the Qual signal becomes invalid (the end condition)).
With respect to claim 8, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the method of claim 7 further comprising:
after detecting the qualifier signal, changing a read pointer to indicate a first memory location of the first set of memory addresses; iteratively updating the read pointer to a next memory address of the first set of memory addresses after the acquisition data is read from the current memory address indicated by the read pointer; after a last memory address of the first set of memory addresses is read, changing the read pointer to indicate a first memory location of the third set of memory addresses; and until a last memory address of the third set of memory addresses is read, iteratively updating the read pointer to a next memory address of the third set of memory addresses after the acquisition data is read from the current memory address indicated by the read pointer (par. 27, the samples are read out of the memory, starting with pre-qualification samples, then qualification samples, then post-qualification samples. Given that the pre-qualification samples, qualification samples and post-qualification samples are read out, this occurs after the qualifier signal).
With respect to claim 10, Montijo teaches a system for using a data buffer for storing acquisition data, the system comprising:
a device comprising:
at least one processor (par. 23, processor 200); and
a buffer controller (par. 23, memory controller 113)
a data buffer (par. 23, memory device is configured to operate as a circular buffer) controllable to operate in a segmented memory mode and a qualified store memory mode (par. 23, qualified store algorithm and par. 3, segmented memory mode), wherein the buffer controller is configured to initially store acquisition data obtained from an oscilloscope in the data buffer (pars. 22-23, memory device is configured to operate as a circular buffer), wherein initially storing the acquisition buffer in the SRAM includes:
during an initial phase and prior to an end condition being met, iteratively providing a write pointer indicating one of a first set of memory locations of a first memory segment of the data buffer, wherein iteratively providing the write pointer includes updating the write pointer to a next memory location of the first set of memory locations in a circular manner after a the acquisition data from the oscilloscope is stored in a current memory location (par. 24 and fig. 2, in the Store Pre-Qual state, the circular buffer is continuously written and rewritten with N digital samples until the qualification signal becomes valid (the end condition of the claim). This is also illustrated in fig. 4, where Location 0 through Location N-1 are iteratively written before circling back to Location 0); and
in response to the end condition being met, changing the write pointer to indicate one of a second set of memory locations of a second memory segment of the data buffer (Pars. 25 and fig. 2, after the qualification signal becomes invalid (the end condition), the device enters the Store Post-Qual state, where data is written linearly into locations in a third portion of the memory device 114 (second segment of the data buffer). This is illustrated in fig. 4, as locations N+X+1 through 2N+X+M-1).
Montijo fails to teach that the data buffer is implemented in SRAM, and transferring the acquisition data from the data buffer in the SRAM to a DRAM.
Bartlett teaches:
a static random access memory (SRAM) including a data buffer, wherein the buffer controller is configured to control the data buffer to initially store acquisition data obtained from an oscilloscope in the data buffer implemented in the SRAM (pars. 33-34, the acquisition memory storing data from the oscilloscope, and par. 42, the acquisition memory may be SRAM);
the system further comprises a dynamic random access memory (DRAM) and the buffer controller is further configured to, in response to the end condition being met, transferring the acquisition data from the data buffer in the SRAM to the DRAM (par. 82, the memory storing trigger events T associated with previously acquired data record, the data record coming from the acquisition memory as described in par. 47, and par. 42, the memory device may be DRAM).
It would have been obvious to one of ordinary skill in the art, having the teachings of Montijo and Bartlett before him before the earliest effective filing date, to modify the memory access method of Montijo with the memory access method of Bartlett, as it would be obvious to try. Bartlett lists the common types of memory used in a computer system, such as SRAM, DRAM, EPROM, EEPROM and flash memory. One of ordinary skill in the art would have been motivated to select from one of these common types of memories, as there are a limited number of common options that would be obvious to try. When there is a design need for market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp (KSR, 82 USPQ2d at 1397). As discussed in Bartlett, pars. 2-5, modern oscilloscopes require more memory than older oscilloscopes, and one of ordinary skill in the art having the teachings of Bartlett before him would choose from one of the listed memory options to meet the memory requirements of the oscilloscope.
Claims 11-17 are system dependent claims that correspond to method dependent claims 2-8, and are rejected using similar logic.
With respect to claim 19, Montijo and Bartlett teach the limitations of the parent claim. Montijo further teaches the system of claim 10 wherein the end condition includes a qualifier signal being detected or asserted; the qualifier signal being no longer detected or de-asserted; detecting that a trigger is being met or satisfied, detecting that a reflected pulse occurred within a particular amount of time after a transmitted pulse; detecting that the reflected pulse occurred at a particular rate or in a particular pattern; determining that a number of post trigger words have been acquired; or detecting that one or more conditions related to an observable signal have occurred (par. 25, the qualifier signal becoming invalid is the end condition, which corresponds to the qualifier signal being no longer detected or de-asserted/detecting that one or more conditions related to an observable signal has occurred).
Claim 20 is a non-transitory computer readable medium that corresponds to method claim 1, and is rejected using similar logic.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Montijo and Bartlett as applied to claims 1 and 10 above, in view of Simionescu et al., US PGPub 2021/0089454.
With respect to claim 9, Montijo and Bartlett teach all limitations of the parent claim, but fail to teach wherein the first memory segment has a size that is equal to or greater than a minimum access granularity value for the DRAM. Simionescu teaches the method of claim 1 wherein the first memory segment has a size that is equal to or greater than a minimum access granularity value for the DRAM (par. 16, when the segment is less than the DRAM access granularity, additional data associated with the segment of data is retrieved to form a new segment at the DRAM access granularity).
It would have been obvious to one of ordinary skill in the art, having the teachings of Montijo, Bartlett and Simionescu before him before the earliest effective filing date, to modify the memory access method of Montijo and Bartlett with the memory access method of Simionescu, because with a segment with larger granularity, less metadata is used to represent the segment of data, and less processing overhead is incurred, as taught by Simionescu in par. 16.
Claim 18 is a system dependent claim that correspond to method dependent claim 9, and is rejected using similar logic.
Response to Arguments
Applicant's arguments filed 10/29/2025 have been fully considered but they are not persuasive. Applicant’s remarks are directed towards Montijo and Simionescu failing to teach that the data buffer is implemented in SRAM, where the data buffer is controllable to operate in a segmented memory mode and a qualified store memory mode, and transferring the acquisition data from the data buffer in the SRAM to a DRAM. These arguments are moot, as the new Bartlett reference has been supplied to teach the features of the SRAM and transferring data from the SRAM to DRAM. Montijo teaches the segmented memory mode and qualified store memory mode, as detailed in the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132