Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on October 30, 2024 is in compliance with time for filing requirements of 3 7 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. The examiner notes that the Non-Patent Literature reference “Office Action of Taiwan Counterpart Application” ha s not been considered because the applicant did not provide a translation of this reference. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 318, 320 in Figure 5 and 416 in Figure 6 E . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1-4 , 6 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Chang et al. (US 11728288 - B2) . Regarding Claim 1: Chang discloses a 3D stack package structure (Fig . 5B), comprising: a first chip (first die; Fig 5B element 100, paragraph 47 ); a second chip (second die; Fig. 5B element 200, paragraph 47 and 54), bonded to the first chip (bonding layer; Fig. 5B elements 40 and 230, paragraph 75) and comprising an interconnect structure (second interconnect structure; Fig. 5B element 210, paragraph 54), the interconnect structure being composed of multiple metal layers (inter-metal dielectric (IMD) layers; Fig. 5B element 114 and 214) and a plurality of vias (metal features/via structures; Figs. 3B and 5B elements 116V, 120V, 162V, 164V) that respectively connect upper and lower layers of the multiple metal layers (Figs. 2A-C and 5B, paragraphs 30-31) ; a through-silicon via, extending through the second chip (TSV structures; Fig. 2E and 5B element 150 and 250, paragraph 59 and 24); and a multi-layer protective structure, disposed within the second chip and surrounding the through-silicon via (intermediate structure; Fig. 2A-E element 110A, paragraphs 33, 34), wherein the multi-layer protective structure comprises multiple protective layers, each having an opening for passage of the through-silicon via (ILD layer and/or IMD layers; Figs. 2A-E elements 112 and 114, paragraph 33) and a plurality of sealing rings, respectively connecting upper and lower layers of the multiple protective layers and surrounding the through-silicon via (guard ring structure; Figs. 2E, 3B, 3C, 5B elements 160 and 260, paragraphs 18, 25, 40 and 54). Regarding Claim 2: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the plurality of sealing rings (guard ring structure; Figs. 2E, 3B, 3C, 5B elements 160 and 260, paragraphs 18, 25, 40 and 54) and the plurality of vias (metal features/via structures; Figs. 3B and 5B elements 116V, 120V, 162V, 164V) in the interconnect structure (second interconnect structure; Fig. 5B element 210, paragraph 54) are formed in a same process (dual-Damascene process [guard rings and via structures]; paragraphs 23, 28 and 29). Regarding Claim 3: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the multiple protective layers (ILD layer and/or IMD layers; Figs. 2A-E elements 112 and 114, paragraph 33) and the multiple metal layers (inter-metal dielectric (IMD) layers; Fig. 5B element 114 and 214) in the interconnect structure (second interconnect structure; Fig. 5B element 210, paragraph 54) are formed in a same process (formed during the formation of a TSV; Figs. 2A-E, paragraphs 33-39). Regarding Claim 4 : Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the multiple protective layers (ILD layer and/or IMD layers; Figs. 2A-E elements 112 and 114, paragraph 33) are in direct contact (Figs. 2A-E, 5B, paragraph s 26, 83, 84) with the through-silicon via (TSV structures; Fig. 2E and 5B element 150 and 250, paragraph s 59 and 24). Regarding Claim 6: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the first chip (first die; Fig 5B element 100, paragraph 47) is hybrid bonded (hybrid bonding process; Fig 5B, paragraph 79) to the second chip (second die; Fig. 5B element 200, paragraph s 47 and 54) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Chang et al. (US 11728288B2) in view of Chang et al. (US 20240387196A1) , hereinafter referred to as “Chang ‘ 196 ” . Regarding Claim 5: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1 , but Chang does not explicitly disclose a structure including a first chip that comprises a first distribution layer, a second chip that comprises a second distribution layer, and a silicon-through via that connects the first distribution layer and the second distribution layer. Chang ‘ 196 discloses a semiconductor structure (Fig. 12A element 195A, paragraph s 57-58), wherein the first chip (Figs. 12A and 13A element 122) comprises a first redistribution layer (Fig. 17 element 206) , the second chip (Fig. 12A element 150) comprises a second redistribution layer (Fig. 17 element 222) , and the through-silicon via [ TSV] ( Fig. 17 element 216) connects the first distribution layer and the second distribution layer (Figs. 12A and 17, elements 122, 150, 195, 216, 206, and 222) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Chang ‘196 to include a first distribution layer on the first chip, a second distribution layer on the second chip, and a TSV that connects the first and second distribution layers because both are directed to analogous semiconductor packages . Doing so allows for improvements in the integration of smaller , stackable semiconductor die packages (Chang ‘ 196, paragraph 2 ). Claim (s) FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 7, 9 -12 , and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Chang et al. (US 11728288B2) in view of Thei et al. (US20190363079A1) . Regarding Claim 7: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the first chip (first die; Fig 5B element 100 ) is bonded (bonding layer; Fig. 5B elements 40 and 230, paragraph 75) to the second chip (second die; Fig. 5B element 200 ). Chang does not explicitly disclose a first chip bonded to a second chip by oxide-oxide bonding. Th ei discloses a 3D integrated circuit ( Fig. 3 element 300), wherein a first chip (first IC die; Fig. 3 element 104a) is bonded to a second chip (second IC die; Fig. 3 element 104b) by oxide-oxide bonding (fusion bonding processes and/or metallic bonding processes; Fig. 2 elements 132 a - b, paragraphs 23 and 48) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Thei such that the first chip is bonded to the second chip by fusion and/or metallic bonding processes, for example, oxide-oxide bonding because both are directed to analogous semiconductor packages . Do ing so allows for the continued improvements in package shrinking and integrated circuit processing capabilities ( Thei , paragraph 1). Regarding Claim 9: Chang discloses a 3D stack package structure (Fig. 5B), comprising: a first chip (first die; Fig 5B element 100, paragraph 47) , comprising a first substrate (a first semiconductor substrate; Fig. 5B element 102, paragraph 84) and a first semiconductor structure formed on the first substrate (a first interconnect structure; Fig. 5B element 110, paragraph 84) ; a plurality of second chips (a second die and a third die; Figs. 5B elements 200 and 300, paragraphs 47 and 62) , each comprising a second substrate (a second semiconductor substrate; Fig. 5B element 202 and 302, paragraph 54) and a second semiconductor structure formed on the second substrate (a second interconnect structure; Fig. 5B element 210 and 310; paragraph 55 and 63) , wherein the second semiconductor structure comprises an interconnect structure composed of multiple metal layers ( ILD layer , IMD layers ; Fig. 5B elements 212 and 214) and a plurality of vias (via structures; Figs. 1 B and 5B elements 116, 116V, 216, 316, paragraph 20) that respectively connect upper and lower layers of the multiple metal layers (Fig. 5B elements 210, 212, 214, 216, and 220, paragraphs 54-55) , the plurality of second chips are bonded to each other (back side and front side bonding layers; Fig. 5B elements 44 and 330, paragraphs 47, 61-62, and 76) ; a through-silicon via , extending through the plurality of second chips (Fig. 5B elements 150, 250, 350, paragraphs 24, 59, and 66) ; and a plurality of multi-layer protective structures (intermediate structure; Fig. 2A-E element 110A ) , respectively disposed within the plurality of second chips and surrounding the through-silicon via ( Fig. 2A-E element 110A, 210, and 310, paragraphs 33, 34, 54-55, and 62-63 ) , wherein each of the multi-layer protective structures comprises: multiple protective layers, each having an opening for passage of the through-silicon via (ILD layer and/or IMD layers; Figs. 2A-E elements 112, 114, 212, 214, 312, and 314, paragraphs 33, 59, and 62) ; and a plurality of sealing rings (guard ring structure; Fig. 5B elements 160, 260, and 360) , respectively connecting upper and lower layers of the multiple protective layers and surrounding the through-silicon via ( Figs. 2E, 3B, 3C, paragraphs 18, 25, 40, 54, and 62 ). However, Chang does not explicitly disclose that the first semiconductor structure of the first chip is bonded to the second semiconductor structure of the second chip. Thei discloses a 3D integrated circuit Fig. 3 element 300 , paragraph 11 ) where the first semiconductor structure (first interconnect structure; Fig. 2 element 108a) of the first chip (first IC die; Fig. 2 element 104a) is bonded (bonding structures; Fig. 2 elements 132a-b, paragraph s 18, 56, and 62) to the second semiconductor structure (second interconnect structure; Fig. 2 element 108b) of the second chip (second IC die; Fig. 2 element 104b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Thei such that the first semiconductor structure on the first chip is bonded to the second semiconductor structure on the second chip because both are directed to analogous semiconductor packages. Doing so improves the power consumption and processing capabilities in a 3D stackable semiconductor package ( Thei , paragraph 1). Regarding Claim 10: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, wherein Chang discloses that a plurality of sealing rings (guard ring structure; Fig. 5B elements 160, 260, and 360) in each of the second chips and a plurality of vias (via structures; Figs. 1B and 5B elements 116, 116V, 216, 316) in the interconnect structure are formed in a same process (dual-Damascene process ; paragraphs 23, 28-29, 54, and 62). Regarding Claim 11: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, wherein Chang discloses that the multiple protective layers in each of the second chips ( ILD layer and/or IMD layers; Figs. 2A-E elements 112, 114, 212, 214, 312, and 314 ) and the multiple metal layers in the interconnect structure ( ILD layer , IMD layers ; Fig. 5B elements 212 and 214) are formed in the same process (formed during the formation of a TSV; Figs. 2A-E, paragraphs 33-39, 54, and 62) . Regarding Claim 12: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, wherein Chang discloses that multiple protective layers in each of the second chips ( ILD layer and/or IMD layers; Figs. 2A-E elements 112, 114, 212, 214, 312, and 314 ) are in direct contact with the through-silicon via (Figs. 2 B -E, 5B elements 2 50, 350, 210 and 310, paragraph s 26, 83, 84 , and 62 ). Regarding Claim 14: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, wherein Chang disclose s the plurality of second chips are bonded to each other ( Fig. 5B elements 44, 330, paragraph 76 ) , but does not explicitly disclos e that the plurality of second chips are bonded to each other by oxide-oxide bonding. Thei disclose s a bonding process between a plurality of chips (Fig. 2 elements 132 a - b, paragraphs 23 and 48) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Thei such that the plurality of second chips are bonded to each other by fusion and/or metallic bonding processes, for example, oxide-oxide bonding because both are directed to analogous semiconductor packages. Do ing so allows for the continued improvements in package shrinking and integrated circuit processing capabilities ( Thei , paragraph 1). Regarding Claim 15: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, wherein Chang discloses that the first chip (first die; Fig 5B element 100 ) is bonded (bonding layer; Fig. 5B elements 40 and 230, paragraph 75) to the second chip (second die; Fig. 5B element 200 ). Chang does not explicitly disclose a first chip bonded to a second chip by oxide-oxide bonding. Thei discloses a first chip (first IC die; Fig. 3 element 104a) is bonded to a second chip (second IC dies; Fig. 3 element 104b) by oxide-oxide bonding (fusion bonding processes and/or metallic bonding processes; Fig. 2 elements 132 a - b, paragraphs 23 and 48) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Thei such that the first chip is bonded to the second chip by fusion and/or metallic bonding processes, for example, oxide-oxide bonding because both are directed to analogous semiconductor packages. Do ing so allows for the continued improvements in package shrinking and integrated circuit processing capabilities ( Thei , paragraph 1). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Chang et al. (US 11728288B2) and Thei et al. (US 20190363079A1) as applied to claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" 9 above, and further in view Chang et al. (US 20240387196A1), hereinafter referred to as “Chang ‘196” . Regarding Claim 13: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9, but Chang does not explicitly disclose a structure including a first chip that comprises a first distribution layer, an outermost second chip among the plurality of second chips that comprises a second distribution layer, and a through-silicon via that connects the first redistribution layer and the second redistribution layer. Chang ‘196 discloses a semiconductor structure (Fig. 13A element 195B, paragraph 58), wherein the first chip (Figs. 13A element 122) comprises a first redistribution layer (Fig. 17 element 206) , the outermost second chip among the plurality of second chips (Fig. 13A element s 150) comprises a second distribution layer (Fig. 17 element 222) , and the through-silicon via (Fig. 17 elements 216) connects the first distribution layer and the second distribution layer (Figs. 13A and 17, elements 122, 150, 195, 216, 206, and 222 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang and Thei further in view of Chang ‘196 to include a first distribution layer on the first chip, a second distribution layer on the outmost second chip among the plurality of second chips, and a TSV that connects the first and second distribution layers because both are directed to analogous semiconductor packages. Doing so allows for improvements in the integration of smaller, stackable semiconductor die packages (Chang ‘196, paragraph 2). Claim FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 8 is rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Chang et al. (US 11728288B2) in view of Kao et al. (US20210391237A1) . Regarding Claim 8: Chang discloses a 3D stack package structure (Fig. 5B) according to claim 1, wherein the second chip (second die; Fig. 5B element 200, paragraph s 47 and 54) further comprises a device isolation structure (isolation structures; Fig. 5B element 102, paragraphs 17 and 54) , but does not explicitly disclose the through-silicon via extends through the isolation device. Kao discloses an integrated chip structure (Fig. 6 element 600, paragraph 5 1), wherein a second chip (second IC tier; Fig. 6 element 202b) further comprises a device isolation structure (Fig. 4A element 410, paragraph s 34 and 38) , and a through-silicon via (Figs. 4A and 6 element 112) extends through the device isolation structure (Figs. 4A and 6 elements 112, 410, and 202a-b, paragraphs 34, 38, and 51) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang further in view of Kao such that the TSV extends through the isolation device structure on the second chip because both are directed to analogous semiconductor packages. Do ing so allows for the mitigation of negative effects such as leakage or chip failure during the construction of integrated circuits ( Kao , paragraph s 14 and 38 ). Claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 16 is rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Chang et al. (US 11728288B2) and Thei et al. (US 20190363079A1) as applied to claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" 9 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Kao et al. (US 20210391237A1) . Regarding Claim 16: The combination of Chang and Thei discloses a 3D stack package structure according to claim 9 , wherein Chang discloses that each of the second chips (a second die and a third die; Figs. 5B elements 200 and 300, paragraphs 47 and 62) further comprises a device isolation structure (isolation structures; Fig. 5B element 102, paragraphs 17 and 54) , but does not explicitly disclose the through-silicon via extends through the isolation device. Kao discloses an integrated chip structure (Fig. 6 element 600, paragraph 51), wherein a second chip (second IC tier; Fig. 6 element 202b) further comprises a device isolation structure (Fig. 4A element 410, paragraph s 34 and 38), and a through-silicon via (Figs. 4A and 6 element 112) extends through the device isolation structure (Figs. 4A and 6 elements 112, 410, and 202a-b, paragraphs 34, 38, and 51). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the 3D package structure described in Chang and Thei further in view of Kao such that the TSV extends through the isolation device structure on each of the second chip s because both are directed to analogous semiconductor packages. Doing so allows for the mitigation of negative effects such as leakage or chip failure during the construction of integrated circuits (Kao, paragraph s 14 and 38 ). Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu et a. (US20230077851 A1), Wen et al. (US20250167077 A1), Ku et al. (US20230163084 A1), Chang et al. (US20230307384 A1), Ku et al. (US20230178589 A1), and Liu et al. (US20210249365 A1) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Chloë E Benton whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-9976 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Thursday: 8am-6pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Zandra Smith can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-2429 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chloë E Benton/ Examiner, Art Unit 2899 /ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899