DETAILED ACTION
This Office Action, based on application 18/539,350 filed 14 December 2023, is filed responsive to applicant’s initial filing of the application. Claims 1-20, as originally filed, are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The following claims are objected to due to informalities:
Claims 4 and 14: Lack of antecedent basis of the term “the timing parameter” in reference to “of second data lines of one sub-channel”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over PORTERFIELD (US PGPub 2009/0019323) in further view of KOSTINSKY et al (US PGPub 2014/0189224).
With respect to Claim 1, PORTERFIELD discloses a method for detecting data lane mapping between a first circuitry (Fig 1, Host Controller 16; Fig 7, circuitry controlling Host Data Path) and a second circuitry (Fig 1, Host Controller 16; Fig 7, circuitry controlling Host Command/Address Path) in a system (Table 10; ¶[0049] – “If the Cfg.LastDQ bit is set, the memory devices 50 decode the TS1 control field to determine which of the six CA Rx lanes are to be mapped to the four DQ Tx lanes”), wherein the first circuitry includes a plurality of first data lanes and the second circuitry includes a plurality of second data lanes and each first data lane is mapped to a different second data lane (Table 10 illustrates CA to DQ lane 1-to-1 mapping for different control fields), and the second circuitry is configured to transfer data between the first circuitry and an external device via the plurality of second data lanes (Abstract – “The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes”), the method comprising:
configuring both the external device and the first circuitry with a specific data pattern (Table 1 illustrates data patterns of a training sequence; ¶[0045] – “The host controller 16 then issues the TS0 training sequence on the CA transmitter … the memory devices 50 generate the TS0 training sequence on their DQ transmitter”);
configuring the second circuitry for transfer of the specific data pattern from the external device to the first circuitry (Table 1 illustrates data patterns of a training sequence; ¶[0045] – “The host controller 16 then issues the TS0 training sequence on the CA transmitter … the memory devices 50 generate the TS0 training sequence on their DQ transmitter”);
performing a data transfer test, wherein the specific data pattern stored in the external device is transferred from the external device to the first circuitry via the plurality of second data lanes during the data transfer test, wherein the data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to a value (¶[0042] – “The protocol rules shown in FIG. 10 include several training states, each of which is described in detail below”; ¶[0049] – “The objectives of the TS1 state 306 are to lane de-skew the CA lanes of the memory devices 50 to allow the host controller 240 to achieve frame-lock on the CA lanes, and properly adjust the timing of internal clock signals. More specifically, during the TS1 state 306, the memory devices 50 map the CA Primary Receive port 80 to the DQ Primary Transmit port 188 to allow the host controller 240 visibility to the CA lane skew. The host controller 16 then de-skews the CA lanes to the slowest lane {analogous to ‘the target second data lane’} by causing the Barrel Shifter 262 to introduce delay on the faster lanes”); and
determining data lane mapping for the target second data lane between the first circuitry and the second circuitry based on results of the data transfer test (Abstract – “The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames”).
PORTERFIELD may not explicitly disclose wherein the timing parameter for the target second data lane is an invalid value.
However, KOSTINSKY discloses wherein the timing parameter for the target second data lane is an invalid value.
PORTERFIELD and KOSTINSKY are analogous art because they are from the same field of endeavor of managing data lanes to memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PORTERFIELD and KOSTINSKY before him or her, to modify the determined timing of the slowest lane of PORTERFIELD to include an ‘invalid’ delay value as taught by KOSTINSKY. A motivation for doing so would have been to recognize that initial Clock/CTRL/CA timings may be invalid depending on standards including the LPDDR-3 standard and related implementations (¶[0031]). Therefore, it would have been obvious to combine PORTERFIELD and KOSTINSKY to obtain the invention as specified in the instant claims.
With respect to Claim 11, PORTERFIELD discloses a processor for detecting data lane mapping between a first circuitry (Fig 1, Host Controller 16; Fig 7, circuitry controlling Host Data Path) and a second circuitry (Fig 1, Host Controller 16; Fig 7, circuitry controlling Host Command/Address Path) in a system (Table 10; ¶[0049] – “If the Cfg.LastDQ bit is set, the memory devices 50 decode the TS1 control field to determine which of the six CA Rx lanes are to be mapped to the four DQ Tx lanes”), wherein the first circuitry includes a plurality of first data lanes and the second circuitry includes a plurality of second data lanes and each first data lane is mapped to a different second data lane (Table 10 illustrates CA to DQ lane 1-to-1 mapping for different control fields), and the second circuitry is configured to transfer data between the first circuitry and an external device via the plurality of second data lanes (Abstract – “The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes”), the processor comprising:
processing circuitry configured to execute software code, wherein the software code is adapted, if executed on the processing circuitry, to:
configure both the external device and the first circuitry with a specific data pattern (Table 1 illustrates data patterns of a training sequence; ¶[0045] – “The host controller 16 then issues the TS0 training sequence on the CA transmitter … the memory devices 50 generate the TS0 training sequence on their DQ transmitter”);
configure the second circuitry for transfer of the specific data pattern from the external device to the first circuitry (Table 1 illustrates data patterns of a training sequence; ¶[0045] – “The host controller 16 then issues the TS0 training sequence on the CA transmitter … the memory devices 50 generate the TS0 training sequence on their DQ transmitter”);
perform a data transfer test, wherein the specific data pattern stored in the external device is transferred from the external device to the first circuitry via the plurality of second data lanes during the data transfer test, wherein the software code is adapted to perform the data transfer test iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to a value (¶[0042] – “The protocol rules shown in FIG. 10 include several training states, each of which is described in detail below”; ¶[0049] – “The objectives of the TS1 state 306 are to lane de-skew the CA lanes of the memory devices 50 to allow the host controller 240 to achieve frame-lock on the CA lanes, and properly adjust the timing of internal clock signals. More specifically, during the TS1 state 306, the memory devices 50 map the CA Primary Receive port 80 to the DQ Primary Transmit port 188 to allow the host controller 240 visibility to the CA lane skew. The host controller 16 then de-skews the CA lanes to the slowest lane {analogous to ‘the target second data lane’} by causing the Barrel Shifter 262 to introduce delay on the faster lanes”); and
determine data lane mapping for the target second data lane between the first circuitry and the second circuitry based on results of the data transfer test (Abstract – “The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames”).
PORTERFIELD may not explicitly disclose wherein the timing parameter for the target second data lane is an invalid value.
However, KOSTINSKY discloses wherein the timing parameter for the target second data lane is an invalid value.
PORTERFIELD and KOSTINSKY are analogous art because they are from the same field of endeavor of managing data lanes to memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PORTERFIELD and KOSTINSKY before him or her, to modify the determined timing of the slowest lane of PORTERFIELD to include an ‘invalid’ delay value as taught by KOSTINSKY. A motivation for doing so would have been to recognize that initial Clock/CTRL/CA timings may be invalid depending on standards including the LPDDR-3 standard and related implementations (¶[0031]). Therefore, it would have been obvious to combine PORTERFIELD and KOSTINSKY to obtain the invention as specified in the instant claims.
With respect to Claim 16, the combination of PORTERFIELD and KOSTINSKY disclose a system on chip (SoC) comprising:
a processor configured to execute memory reference code (MRC);
a memory controller including a plurality of first data lanes; and
a physical layer (PHY) circuitry including a plurality of second data lanes, wherein each first data lane in the memory controller is mapped to a different second data lane in the PHY circuitry and the PHY circuitry is configured to transfer data between the memory controller and a memory module via the plurality of second data lanes,
wherein the MRC is configured, if executed on the processor, to perform the method of claim 1 (See Grounds of Rejection issued to Claim 1 above).
With respect to Claim 20, the combination of PORTERFIELD and KOSTINSKY disclose a non-transitory machine-readable medium including code, when executed, to cause a machine to perform the method of claim 1 (See Grounds of Rejection issued to Claim 1 above).
With respect to Claims 2 and 12, the combination of PORTERFIELD and KOSTINSKY disclose the method/processor of each respective parent claim.
PORTERFIELD further discloses wherein the timing parameters are phase-locked loop (PLL) delay values for the second data lanes in the second circuitry (Fig 7, PLL 244; ¶[0032] – “The receiver 242 applies the clock signal to a PLL 244, which generates four-phases of an internal clock signal. The PLL 244 also generates and outputs from a CA Primary Clock port 246 four-phases of a CA Primary Clock signal, which are received from a transmitter 248”).
With respect to Claim 19, the combination of PORTERFIELD and KOSTINSKY disclose the SoC of claim 16.
PORTERFIELD further discloses wherein the MRC is configured to adjust phase-locked loop (PLL) delay values for the second data lanes in the second circuitry to perform the data transfer test (¶[0036] – “The barrel shifter 262, PLL 244, SDL 254 and Rx Framing Logic 291 are controlled during initialization by a Link Initialization module 292. This initialization is performed after minor signal skews in the 6 CA lanes from the CA Primary Transmit port 274 of the host controller 240 of less than one unit interval ("UI") in duration have been corrected to achieve "bit lock." Bit lock refers to ensuring that relatively small CA signal skews in the CA lanes from the port 274 of less than one UI have been corrected. This correction is accomplished in the host controller 240 by adjusting the timing at which command and address bits on each of the 6 CA lanes are clocked out of the registers 268 and transmitted from the CA Primary Transmit port 274. Similarly, the below-described initialization is performed after minor signal skews in the 4 DQ lanes from the DQ Primary Transmit port 190 of the memory devices 50 of less than one unit interval ("UI") in duration have been corrected to achieve "bit lock." This correction is accomplished in the host controller 240 by adjusting the timing at which read data bits on each of the 4 DQ lanes are captured by the latches 288”).
With respect to Claims 3 and 13, the combination of PORTERFIELD and KOSTINSKY disclose the method/processor of each respective parent claim.
PORTERFIELD further discloses wherein the second circuitry includes control registers and the timing parameters for the second data lanes are controlled by using the control registers (¶[0039] – “As with the memory device 50, the host controller 240 includes a Register 293 that receives configuration data through the Side Band access bus 34 (FIG. 1) and a buffer 294. The Register 293 can also apply Configuration data to the Side Band access bus 34 through a second buffer 295”).
With respect to Claims 4 and 14, the combination of PORTERFIELD and KOSTINSKY disclose the method/processor of each respective parent claim.
PORTERFIELD further discloses wherein the first data lanes and the second data lanes are divided into two or more sub-channels, and the timing parameter of second data lanes of one sub-channel is set to the invalid value and the timing parameters for the second data lanes of all other sub-channels in the second circuitry are adjusted in the pre-configured range, such that a sub-channel mapping between the first circuitry and the second circuitry is determined based on the results of the data transfer test (¶[0042] – “The protocol rules shown in FIG. 10 include several training states, each of which is described in detail below”; ¶[0049] – “The objectives of the TS1 state 306 are to lane de-skew the CA lanes of the memory devices 50 to allow the host controller 240 to achieve frame-lock on the CA lanes, and properly adjust the timing of internal clock signals. More specifically, during the TS1 state 306, the memory devices 50 map the CA Primary Receive port 80 to the DQ Primary Transmit port 188 to allow the host controller 240 visibility to the CA lane skew. The host controller 16 then de-skews the CA lanes to the slowest lane by causing the Barrel Shifter 262 to introduce delay on the faster lanes” – Each CA[x] => DQ[x] analogous to a ‘sub-channel’).
With respect to Claim 18, the combination of PORTERFIELD and KOSTINSKY disclose the SoC of claim 16.
PORTERFIELD further discloses wherein the first data lanes and the second data lanes are divided into two or more sub-channels (¶[0042] – “The protocol rules shown in FIG. 10 include several training states, each of which is described in detail below”; ¶[0049] – “The objectives of the TS1 state 306 are to lane de-skew the CA lanes of the memory devices 50 to allow the host controller 240 to achieve frame-lock on the CA lanes, and properly adjust the timing of internal clock signals. More specifically, during the TS1 state 306, the memory devices 50 map the CA Primary Receive port 80 to the DQ Primary Transmit port 188 to allow the host controller 240 visibility to the CA lane skew. The host controller 16 then de-skews the CA lanes to the slowest lane by causing the Barrel Shifter 262 to introduce delay on the faster lanes” – Each CA[x] => DQ[x] analogous to a ‘sub-channel’), and the MRC is configured to determine a sub-channel mapping between the first circuitry and the second circuitry is determined based on the results of the data transfer test (Table 10; ¶[0049] – “If the Cfg.LastDQ bit is set, the memory devices 50 decode the TS1 control field to determine which of the six CA Rx lanes are to be mapped to the four DQ Tx lanes”).
With respect to Claims 5 and 15, the combination of PORTERFIELD and KOSTINSKY disclose the method/processor of each respective parent claim.
PORTERFIELD further discloses wherein the determination of the data lane mapping between the first circuitry and the second circuitry is performed during a boot up of the system (¶[0004] – ”There is therefore a need for an initialization system and method that can, for example, relatively inexpensively initialize a memory system that couples data to and from memory devices through high-speed buses”).
With respect to Claim 6, the combination of PORTERFIELD and KOSTINSKY disclose the method of claim 1.
PORTERFIELD further discloses wherein the data transfer test is performed by: sending a request to the external device; receiving the specific data pattern sent from the external device on the first data lanes; comparing the specific data pattern received from the external device to the specific data pattern stored in the first circuitry; and recording a comparison result for each first data lane in a register (¶[0042] – “The protocol rules shown in FIG. 10 include several training states, each of which is described in detail below. It is the responsibility of the host controller 16 to transition the system through the training states. These training states are a Disable state 300, in which the communication to and from the host controller 16 is inactive. The second training state is a "TS0" state 304 in which the host controller 16 and the memory device 50 bit-lock each lane, the host controller 16 perform lane de-skew on its own bit lanes, and the host controller 16 frame-locks the read data. The third training state it a "TS1" state 306 in which the host controller 16 achieves frame-lock of the command/address bits, as explained above. As explained above, the command/address bits are bits of the command/address bus that contain a memory command or a memory address. The next training state is a "TS2" state 308 in which the memory device calculates a "DQ merge" if necessary, as described in greater detail below. The fifth training state is a "TS3" state 310 in which user defined test patterns are generated, as also described in greater detail below. The sixth training state is a "L0" state 314 in which the host controller 16 and memory devices 50 are active and frame packets are passed between the memory devices 50 and the host controller 16. The final state is a "Calibrate" state 318 in which the host controller 16 and the memory devices 50 perform receiver offset calibrations using the technique described above”).
With respect to Claim 7, the combination of PORTERFIELD and KOSTINSKY disclose the method of claim 1.
PORTERFIELD further discloses wherein the first circuity is a memory controller of a memory sub-system, and the second circuitry is physical layer (PHY) circuitry of the memory sub-system (Fig 1, Host Controller 16; Fig 7).
With respect to Claim 8, the combination of PORTERFIELD and KOSTINSKY disclose the method of claim 7.
PORTERFIELD further discloses wherein the memory controller and the PHY circuitry are integrated into a system on chip (SoC) (Fig 1, System 10).
With respect to Claim 9, the combination of PORTERFIELD and KOSTINSKY disclose the method of claim 7.
KOSTINSKY further discloses wherein the method is implemented by basic input/output system (BIOS) memory reference code (MRC) (¶[0015] – “Low-Power DDR-3 (LPDDR-3) command/address (CA) training mode and mode register readout (MRR) require specific data (DQ) pin mapping if there is swapping on the board. Not allowing swapping on the board restricts options to system designers and manufacturers by limiting product options and increasing design complexity. For example, mapping of all 128 DQ pins for a typical two-channel LPDDR3 embodiment would require significant human effort and may result in errors. It may also require a custom BIOS/MRC (Memory Reference Code) version for each board and for each memory configuration option, resulting in complex production environments and complex production management issues”).
With respect to Claims 10 and 17, the combination of PORTERFIELD and KOSTINSKY disclose the method of claim 7.
KOSTINSKY further discloses wherein the memory controller and the PHY circuitry are compliant to Fifth Generation Double Data Rate (DDR5) standards (¶[0034] – “Described herein are techniques for training Control signals timings that are particularly useful for LPDDR3; however, other memory devices can also be supported”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach related mappings of data lanes/lines.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
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/ERIC T LOONAN/Primary Examiner, Art Unit 2137
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