DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 11-15, 18, and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takeda (U.S. Pub. No. 20260012715).
Regarding claim 1, Takeda discloses:
An image sensor comprising:
a first die including a pixel array area in which first and second photoelectric conversion devices configured to generate respective charges corresponding to incident light are disposed (light receiving chip 201 is provided with a light reception unit 220 with a plurality of photodiodes 221, that photoelectrically convert incident light to generate a photocurrent, are arrayed in a two-dimensional lattice manner including a first pixel PnL, a second pixel PnR (PnL and PnR are first photoelectric conversion devices), and a normal pixel 222 (second photoelectric conversion devices) including photodiodes 221, where image plane phase difference AF processing is achieved by using luminance signals from the first and second pixels PnL and PnR, and where for normal pixels 222 address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event, par. 53, 54, 56, 94, 95, 109, 154-158, 163, and Figs. 9 and 13); and
a second die (detection chip 202 is provided with via arrangement parts 231 to 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, an address event detection unit 260 (which includes address event detection circuit 300), and a bias supply unit 270, par. 55, 61, 70, 163, and Figs. 5-7 and 15) including a first pixel circuit configured to receive the charges from the first photoelectric conversion device and generate a phase signal of the incident light based on the charges received from the first photoelectric conversion device (event detection circuit 300 corresponding to pixels PnL and PnR output a digital signal Vcm according to the photocurrent from the corresponding photodiode 221 in order to execute the image plane phase difference AF, par. 61 and 109), and a second pixel circuit configured to receive the charges from the second photoelectric conversion device and generate an event signal corresponding to the incident light based on the charges received from the second photoelectric conversion device (event detection circuit 300 corresponding to normal pixels 222, where address event detection circuit 300 quantizes a voltage signal according to the photocurrent from the corresponding photodiode 221 and outputs the same as the detection signal, where address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event, par. 56, 61).
Regarding claim 8, Takeda further discloses:
a first connection structure configured to connect the first photoelectric 40 conversion device and the first pixel circuit and disposed in an area in which the pixel array area and the first pixel circuit overlap (for the first pixel PnL and second pixel PnR, chips 201 and 202 are bonded by a via or the like, and they may also be joined to each other by Cu—Cu joint or a bump in addition to the via, where each of the address event detection circuits 300 to which a pixel address is assigned is connected to the photodiode 221 having the same address, par. 52-56, 61); and
a second connection structure configured to connect the second photoelectric conversion device and the second pixel circuit and disposed in an area in which the pixel array area and the second pixel circuit overlap (for the normal pixels 222, chips 201 and 202 are bonded by a via or the like, and they may also be joined to each other by Cu—Cu joint or a bump in addition to the via, where each of the address event detection circuits 300 to which a pixel address is assigned is connected to the photodiode 221 having the same address, par. 52-56, 61).
Regarding claim 11, Takeda further discloses:
first connection structure and the second connection structure are at least one of an electrical line, a wire, a solder ball, a bump, and a through silicon via (TSV) (n the via arrangement parts 211 to 213, vias (for example, through silicon via (TSV)) connected to the detection chip 202 are arranged and in the via arrangement parts 231 to 233, vias (for example, TSVs) connected to the light receiving chip 201 are arranged, par. 54-55).
Regarding claim 12, Takeda further discloses:
the first photoelectric conversion device and the second photoelectric conversion device are disposed adjacent to each other (first pixel PnL and the second pixel PnR are arranged adjacent to the normal pixel 222, and are alternately arranged substantially evenly, par. 97 and Figs. 9 and 13), and
wherein one micro lens disposed on the first photoelectric conversion device and the second photoelectric conversion device is further included (on-chip lens OCL is provided corresponding to each normal pixel 22 and the first and second pixels PnL and PnR adjacent to each other provided in one normal pixel 222 correspond to one on-chip lens OCL, par. 160).
Regarding claim 13, Takeda further discloses:
a mask layer disposed on the first photoelectric conversion device and of which a first or second side is shielded (first pixel PnL (n is a positive integer) has a light-shielded part on one side, and photoelectrically converts incident light from an exception part to generate a first current and second pixel PnR has a light-shielded part on a side opposite to the light-shielding part of the first pixel PnL, and photoelectrically converts incident light from an exception part to generate a second current, par. 95 and 96).
Regarding claim 14, Takeda discloses:
An image sensor comprising:
a phase detection pixel including a first photoelectric conversion device configured to generate charges corresponding to incident light, and a first pixel circuit configured to generate an output voltage corresponding to the charges received from the first photoelectric conversion device and a phase signal of the incident light (light receiving chip 201 is provided with a light reception unit 220 with a plurality of photodiodes 221, that photoelectrically convert incident light to generate a photocurrent, are arrayed in a two-dimensional lattice manner including a first pixel PnL, a second pixel PnR (PnL and PnR are first photoelectric conversion devices), and a normal pixel 222 (second photoelectric conversion devices) including photodiodes 221, where image plane phase difference AF processing is achieved by using luminance signals from the first and second pixels PnL and PnR, par. 53, 54, 56, 94, 95, 109, 154-158, 163, and Figs. 9 and 13); and
a dynamic vision sensor (DVS) pixel including a second photoelectric conversion device configured to generate charges corresponding to incident light, and a second pixel circuit configured to generate an event signal by detecting a change in intensity of the incident light based on the charges received from the second photoelectric conversion device (for normal pixels 222 address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event, par. 53, 54, 56, 94, 95, 109, 154-158, 163, and Figs. 9 and 13).
Regarding claim 15, Takeda further discloses:
a first logic circuit configured to receive the phase signal from the first pixel circuit (AD conversion circuit 370 as a current comparison circuit compares a luminance current Ipda by the luminance signal Vcp with a reference current Iref by a reference signal (reference voltage) Vref, and performs analogue-to-digital (AD) conversion on the luminance signal Vcp into a digital signal and the first and second AD conversion circuits 370 can output the digital signal Vcm according to the current Ipda according to the photocurrent Ipd of the first and second pixels PnL and PnR, respectively, where luminance circuit 360 of event detection circuit 300 is connected to the current-voltage conversion circuit 310, and generates a luminance signal Vcp according to the photocurrent from the photodiode 221 corresponding to each pixe, par. 68, 69, 114);
a second logic circuit configured to receive the event signal from the second pixel circuit (transfer circuit 350 transfers the detection signal from the quantizer 340 to the signal processing circuit 240 of event detection circuit 300, par. 67); and
an image signal processor (ISP) configured to receive data output from the first logic circuit and the second logic circuit (control unit 130 can adapt the focal position F to the light receiving surface of the light reception unit 220 by adjusting the focal position so that the array of the digital signals Vcm from the first pixel PnL and the array of the digital signals Vcm from the second pixel PnR are substantially identical and as a result, the control unit 130 can easily focus the incident light on the light receiving surface of the light reception unit 220 and the signal processing circuit 240 processes a digital signal Vcm from an address event detection circuit 300 in FIG. 6, and outputs the digital signal Vcm to the control unit 130, par. 59, 143).
Regarding claim 18, Takeda further discloses:
first photoelectric conversion device and the second photoelectric conversion device are disposed on a semiconductor die (light receiving chip 201 is provided with a light reception unit 220 with a plurality of photodiodes 221, that photoelectrically convert incident light to generate a photocurrent, are arrayed in a two-dimensional lattice manner including a first pixel PnL, a second pixel PnR (PnL and PnR are first photoelectric conversion devices), and a normal pixel 222 (second photoelectric conversion devices) including photodiodes 221, where image plane phase difference AF processing is achieved by using luminance signals from the first and second pixels PnL and PnR, and where for normal pixels 222 address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and , par. 53, 54, 56, 94, 95, 109, 154-158, 163, and Figs. 9 and 13) different from a semiconductor die on which the first pixel circuit and the second pixel circuit are disposed (detection chip 202 is provided with via arrangement parts 231 to 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, an address event detection unit 260, and a bias supply unit 270, par. 55, 61, 70, 163, and Figs. 5-7 and 15).
Regarding claim 19, Takeda further discloses:
first pixel circuit and the second pixel circuit are disposed on the same semiconductor die (detection chip 202 is provided with via arrangement parts 231 to 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, an address event detection unit 260 (which includes address event detection circuit 300), and a bias supply unit 270, par. 55, 61, 70, 163, and Figs. 5-7 and 15, where event detection circuit 300 corresponding to normal pixels 222, where address event detection circuit 300 quantizes a voltage signal according to the photocurrent from the corresponding photodiode 221 and outputs the same as the detection signal, where address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event and event detection circuit 300 corresponding to pixels PnL and PnR output a digital signal Vcm according to the photocurrent from the corresponding photodiode 221 in order to execute the image plane phase difference AF, par. 56, 61, 109).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeda (U.S. Pub. No. 20260012715).
Regarding claim 20, Takeda discloses:
An image sensor comprising:
a first semiconductor die including a first photoelectric conversion device and a second photoelectric conversion device that convert an optical signal into an electrical signal (light receiving chip 201 is provided with a light reception unit 220 with a plurality of photodiodes 221, that photoelectrically convert incident light to generate a photocurrent, are arrayed in a two-dimensional lattice manner including a first pixel PnL, a second pixel PnR (PnL and PnR are first photoelectric conversion devices), and a normal pixel 222 (second photoelectric conversion devices) including photodiodes 221, where image plane phase difference AF processing is achieved by using luminance signals from the first and second pixels PnL and PnR, and where for normal pixels 222 address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event, par. 53, 54, 56, 94, 95, 109, 154-158, 163, and Figs. 9 and 13); and
a second semiconductor die (detection chip 202 is provided with via arrangement parts 231 to 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, an address event detection unit 260 (which includes address event detection circuit 300), and a bias supply unit 270, par. 55, 61, 70, 163, and Figs. 5-7 and 15) that includes:
a first pixel circuit (event detection circuit 300 corresponding to pixels PnL and PnR output a digital signal Vcm according to the photocurrent from the corresponding photodiode 221 in order to execute the image plane phase difference AF, par. 61 and 109); and
a second pixel circuit that includes an output logic circuit generating an event signal by detecting a change in intensity of an optical signal based on the electrical signal received from the second photoelectric conversion device (event detection circuit 300 corresponding to normal pixels 222, where address event detection circuit 300 quantizes a voltage signal according to the photocurrent from the corresponding photodiode 221 and outputs the same as the detection signal, where address event detection unit 260 generates a detection signal from the photocurrent of each of the plurality of photodiodes 221 and outputs the same to the signal processing circuit 240, where the detection signal is a 1-bit signal indicating whether or not a fact that a light amount of the incident light exceeds a predetermined threshold value is detected as an address event, par. 56, 61).
Takeda is silent with regards to the first pixel circuit including a first transistor transmitting the electrical signal received from the first photoelectric conversion device to a floating diffusion node, a second transistor having a gate electrode connected to the floating diffusion node, a third transistor resetting the floating diffusion node. Official Notice is taken that it was well known before the effective filing date of the claimed invention to include a pixel circuit connected to a pixel that includes a first transistor transmitting the electrical signal received from the first photoelectric conversion device to a floating diffusion node, a second transistor having a gate electrode connected to the floating diffusion node, a third transistor resetting the floating diffusion node. This is advantageous in that photoelectric charge can be selectively transferred from a pixel to a floating diffusion for amplification and readout and that pixel circuits can be reset between exposures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include first pixel circuit including a first transistor transmitting the electrical signal received from the first photoelectric conversion device to a floating diffusion node, a second transistor having a gate electrode connected to the floating diffusion node, a third transistor resetting the floating diffusion node.
Allowable Subject Matter
Claims 2-7, 9, 10, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, no prior art could be located that teaches or fairly suggests a third die including a first logic circuit configured to receive the phase signal from the first pixel circuit, a second logic circuit configured to receive the event signal from the second pixel circuit, and an image signal processor (ISP) configured to receive data outputted from the first logic circuit and the second logic circuit, in combination with the rest of the limitations of the claim and parent claim.
Claims 3-7 depend on claim 2 and therefore are objected to.
Regarding claim 9, no prior art could be located that teaches or fairly suggests a first switch including one end electrically connected to the second connection structure and the other end electrically connected to the second pixel circuit; and a second switch including one end electrically connected between the first connection structure and the first pixel circuit and the other end electrically connected to one end of the first switch, in combination with the rest of the limitations of the claim and parent claims.
Claim 10 depends on claim 9 and therefore is objected to.
Regarding claim 16, no prior art could be located that teaches or fairly suggests image signal processor generates a signal that controls: a first mode in which the first photoelectric conversion device is connected to the first pixel circuit and the second photoelectric conversion device is connected to the second pixel circuit, a second mode in which the first photoelectric conversion device is connected to the second pixel circuit, and a third mode in which the second photoelectric conversion device is connected to the first pixel circuit, in combination with the rest of the limitations of the claim and parent claims.
Claim 17 depends on claim 16 and therefore is objected to.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING).
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639
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