DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11-14, 17-19 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (U.S. Patent 9,473,134) in view of Hsu et al. (U.S. Patent 11,177,774, hereafter Hsu).
Claim 1: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD and ND); and
an output driver circuit (504) having an input coupled to the output of the pre-driver circuit and generates a linear driver output signal (108; Figures 3a and 3b where 102 corresponds to the circuitry of Figure 5).
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are part of a translinear loop.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in an open-loop (no feedback in Figures 3A, 4A and 5) common-drain class-AB push-pull configuration (to 133) and generates from the pre-driver output signal a linear driver output signal (Vo) to drive a capacitive load (load connected to Figure 5), wherein the first transistor and the second transistor are part of a translinear loop (via 310 and 410, shown in detail in Figures 3A and 4A where the loop comprises P1, P2 in 310, N2 in 410 and N1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 2: The combined circuit further teaches a third transistor (P2; Figure 3A of Hsu) and a fourth transistor (N2; Figure 4A of Hsu), a gate and a drain of the third transistor being directly connected to each other (Figure 3A), and a gate and a drain of the fourth transistor being directly connected to each other (Figure 4A).
Claim 3: The combined circuit further teaches a first resistor-capacitor circuit (C2, R2; Figure 5 of Hsu) connected between the drain of the third transistor (via VB2) and the gate of the first transistor (via 132), and a second resistor-capacitor circuit (C1, R1) connected between the drain of the fourth transistor (via VB1) and the gate of the second transistor (via 131).
Claim 4. The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) coupled between the output of the pre-driver circuit (via VB2) and a gate of the first transistor (VIN) that corresponds to a first input of the output driver circuit, and a second capacitor (C1) coupled between the output of the pre-driver circuit (via VB1) and a gate of the second transistor that corresponds to a second input of the output driver circuit (VIN).
Claim 5: The combined circuit further teaches that the third transistor and the fourth transistor are part of the pre-driver circuit (and also form part of the translinear loop (310 and 410; Figure 5 of Hsu where the output driver is 130 of Hsu).
Claim 11: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD, ND); and
an output driver circuit (504) having an input coupled to the output of the pre-driver circuit (PD, ND) and generates a linear driver output signal (108; Figures 3a and 3b where 102 corresponds to the circuitry of Figure 5).
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in an open-loop (no feedback in Figures 3A, 4A and 5) common-drain push-pull configuration (to 133) and generates from the pre-driver output signal a driver output signal (Vo) to drive a capacitive load (load connected to Figure 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 12. The combined circuit further teaches a third transistor (P2; Figure 3A of Hsu) and a fourth transistor (N2; Figure 4A of Hsu), a gate and a drain of the third transistor being directly connected to each other (Figure 3A), and a gate and a drain of the fourth transistor being directly connected to each other (Figure 4A), wherein the first transistor, the second transistor, the third transistor and the fourth transistor form a translinear loop (via 310 and 410, shown in detail in Figures 3A and 4A where the loop comprises P1, P2 in 310, N2 in 410 and N1).
Claim 13: The combined circuit further teaches a first resistor-capacitor circuit (C2, R2; Figure 5 of Hsu) connected between the drain of the third transistor (via VB2) and the gate of the first transistor (via 132), and a second resistor-capacitor circuit (C1, R1) connected between the drain of the fourth transistor (via VB1) and the gate of the second transistor (via 131).
Claim 14: The combined circuit further teaches that the third transistor and the fourth transistor are part of the pre-driver circuit (and also form part of the translinear loop (310 and 410; Figure 5 of Hsu where the output driver is 130 of Hsu).
Claim 17: The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) coupled between the output of the pre-driver circuit (via VB2) and a gate of the first transistor (VIN) that corresponds to a first input of the output driver circuit, and a second capacitor (C1) coupled between the output of the pre-driver circuit (via VB1) and a gate of the second transistor that corresponds to a second input of the output driver circuit (VIN).
Claim 18: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD, ND); and
a output driver circuit (504) and generates a linear driver output signal (108; Figures 3a and 3b where 102 corresponds to the circuitry of Figure 5).
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in an open-loop (no feedback in Figures 3A, 4A and 5) common-drain push-pull configuration (to 133), each of the first transistor and the second transistor having a gate that is coupled to the output of the pre-driver circuit (via VIN). and generates from the pre-driver output signal a driver output signal (Vo) at an output corresponding to a node connected to a drain of the first transistor and to a drain of the first transistor (via Vo at 133).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 19: The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) connected between the output of the pre-driver circuit (via VIN) and the gate of the first transistor (P1), and a second capacitor (C1) connected between the output of the pre-driver circuit (via VIN) and the gate of the second transistor (N1).
Claim 22: The combined circuit further teaches that an amplitude of the linear driver output is limited to one threshold voltage of the first transistor or one threshold voltage of the second transistor (Figure 5 of Hsu, where when P1 is on, Vo is supplied by VDD minus the threshold voltage of P1).
Claim 23: The combined circuit further teaches that the pre-driver circuit (502 of Vashishtha; Figure 5 and shown in further detail in Figure 6) includes a cascaded inverter with a first inverter (600) and a second inverter (602), the second inverter having a shorted input to output (via 614).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha in view of Hsu and further in view of Ogata et al. (U.S. Patent 10,256,999, hereafter Ogata).
Claim 24: Vashishtha and Hsu teach the limitations of claim 1 above. Vashishtha and Hsu do not specifically teach an optical modulator having an electrical input coupled to the linear driver output signal.
Ogata teaches an optical modulator (Figure 7A) having an electrical input (input to modulator) coupled via the capacitive load (Figure 3a of Vashishtha to OUT) to the linear driver output signal (Vout via the CMOS driver, corresponding to the output OUT of Figure 5 of Vashishtha).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the optical modulator taught by Ogata in the circuit of Vashishtha and Hsu to stabilize the frequency characteristic of the optical modulator (column 6 lines 3-20).
Response to Arguments
Applicant's arguments filed April 20, 2026 have been fully considered but they are not persuasive.
Applicant asserts that neither Vashishtha nor Hsu teach an open-loop common-drain class-AB push-pull configuration, or generating a linear driver output signal. Examiner respectfully disagrees. In the combined circuit, Vashishtha teaches an output driver circuit (504) having an input coupled to the output of the pre-driver circuit and generates a linear driver output signal (108; Figures 3a and 3b where 102 corresponds to the circuitry of Figure 5). Hsu teaches an open-loop (no feedback in Figures 3A, 4A and 5) common-drain class-AB push-pull configuration (to 133).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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