DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-10, 15, 16, 20 and 21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 12, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11-14 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vashishtha (U.S. Patent 9,473,134) in view of Hsu et al. (U.S. Patent 11,177,774, hereafter Hsu).
Claim 1: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD and ND); and
an output driver circuit (504) having an input coupled to the output of the pre-driver circuit.
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are part of a translinear loop.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in a common-drain class-AB push-pull configuration (to 133) and generates from the pre-driver output signal a driver output signal (Vo) to drive a capacitive load (load connected to Figure 5), wherein the first transistor and the second transistor are part of a translinear loop (via 310 and 410, shown in detail in Figures 3A and 4A where the loop comprises P1, P2 in 310, N2 in 410 and N1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 2: The combined circuit further teaches a third transistor (P2; Figure 3A of Hsu) and a fourth transistor (N2; Figure 4A of Hsu), a gate and a drain of the third transistor being directly connected to each other (Figure 3A), and a gate and a drain of the fourth transistor being directly connected to each other (Figure 4A).
Claim 3: The combined circuit further teaches a first resistor-capacitor circuit (C2, R2; Figure 5 of Hsu) connected between the drain of the third transistor (via VB2) and the gate of the first transistor (via 132), and a second resistor-capacitor circuit (C1, R1) connected between the drain of the fourth transistor (via VB1) and the gate of the second transistor (via 131).
Claim 4. The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) coupled between the output of the pre-driver circuit (via VB2) and a gate of the first transistor (VIN) that corresponds to a first input of the output driver circuit, and a second capacitor (C1) coupled between the output of the pre-driver circuit (via VB1) and a gate of the second transistor that corresponds to a second input of the output driver circuit (VIN).
Claim 5: The combined circuit further teaches that the third transistor and the fourth transistor are part of the pre-driver circuit (and also form part of the translinear loop (310 and 410; Figure 5 of Hsu where the output driver is 130 of Hsu).
Claim 11: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD, ND); and
an output driver circuit (504) having an input coupled to the output of the pre-driver circuit (PD, ND).
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in a common-drain push-pull configuration (to 133) and generates from the pre-driver output signal a driver output signal (Vo) to drive a capacitive load (load connected to Figure 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 12. The combined circuit further teaches a third transistor (P2; Figure 3A of Hsu) and a fourth transistor (N2; Figure 4A of Hsu), a gate and a drain of the third transistor being directly connected to each other (Figure 3A), and a gate and a drain of the fourth transistor being directly connected to each other (Figure 4A), wherein the first transistor, the second transistor, the third transistor and the fourth transistor form a translinear loop (via 310 and 410, shown in detail in Figures 3A and 4A where the loop comprises P1, P2 in 310, N2 in 410 and N1).
Claim 13: The combined circuit further teaches a first resistor-capacitor circuit (C2, R2; Figure 5 of Hsu) connected between the drain of the third transistor (via VB2) and the gate of the first transistor (via 132), and a second resistor-capacitor circuit (C1, R1) connected between the drain of the fourth transistor (via VB1) and the gate of the second transistor (via 131).
Claim 14: The combined circuit further teaches that the third transistor and the fourth transistor are part of the pre-driver circuit (and also form part of the translinear loop (310 and 410; Figure 5 of Hsu where the output driver is 130 of Hsu).
Claim 17: The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) coupled between the output of the pre-driver circuit (via VB2) and a gate of the first transistor (VIN) that corresponds to a first input of the output driver circuit, and a second capacitor (C1) coupled between the output of the pre-driver circuit (via VB1) and a gate of the second transistor that corresponds to a second input of the output driver circuit (VIN).
Claim 18: Vashishtha teaches an apparatus (Figure 5) comprising:
a pre-driver circuit (502) configured to receive an analog input signal (IN) and amplify the analog input signal to generate at an output a pre-driver output signal (PD, ND); and
a output driver circuit (504).
Vashishtha does not specifically teach that the output driver comprises a first transistor and a second transistor.
Hsu teaches an output driver (Figures 3A, 4A and 5 connected to each input PD and ND of Vashishtha) wherein the output driver circuit comprises a first transistor (P1; Figure 5) and a second transistor (N1) connected in a common-drain push-pull configuration (to 133), each of the first transistor and the second transistor having a gate that is coupled to the output of the pre-driver circuit (via VIN). and generates from the pre-driver output signal a driver output signal (Vo) at an output corresponding to a node connected to a drain of the first transistor and to a drain of the first transistor (via Vo at 133).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output driver taught by Hsu in the circuit of Vashishtha to increase reliability of the circuit (column 1 lines 13-23 and column 6 lines 48-53).
Claim 19: The combined circuit further teaches a first capacitor (C2; Figure 5 of Hsu) connected between the output of the pre-driver circuit (via VIN) and the gate of the first transistor (P1), and a second capacitor (C1) connected between the output of the pre-driver circuit (via VIN) and the gate of the second transistor (N1).
Conclusion
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849