Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter Claims 9 -20 are allowed. In regards to claims 9 and 1 5 the representative prior art is Solgun et al., US Patent Application (20210305315) and Yohannes et al., US Patent Application (20220237495), which alone, or in combination, do not provide a teaching, a suggestion or a motivation that could be found either in the art or within the skill of one of ordinary skill in the art at the time of the invention to modify or combine the prior art to disclose the cited claim limitations , more specifically : regarding claim 9 - “ the first electrical path comprises a tunable coupler, which is serially connected in the first electrical path, and which is configured to control interactions between the first quantum bit and the second quantum bit; and the second electrical path is capacitively coupled to the tunable coupler ” and regarding claim 15 – “ wherein the differential coupling bus comprises a first electrical path which capacitively couples the first pad and the third pad, and a second electrical path which capacitively couples the third pad and the fourth pad; wherein the tunable coupler is capacitively coupled to both the first electrical path and the second electrical path ” of the claimed invention. Claims 10 -1 4 and 16-20 depend from claims 9 and 1 5 respectively, and as such the claims are allowed. Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Solgun et al., US Patent Application (20210305315), hereinafter “ Solgun ” Regarding claim 1 Solgun teaches a package structure, comprising: a first quantum bit chip and a second quantum bit chip the term “plane” is used herein to describe one or more groups of layers, such as those of quantum chips. The two circuit planes can be on separate chips in a flip chip geometry, where the second circuit plane on a second chip is bonded to the first quantum circuit plane on a first chip via bump bonds. [ Solgun para 0039] bonded to an interposer the second circuit plane (e.g., interposer chip [ Solgun para 00 40 ] ) ; and a differential coupling bus configured to differentially couple the first quantum bit chip and the second quantum bit chip qubits 240 and 242 are coupled to the coupled-line bus 220 in a differential way [ Solgun para 00 41 ] ) ; at least in part through differential transmission lines disposed on the interposer. the interposer chip includes the control and/or readout resonators/lines for one or more qubits. [ Solgun para 003 2 ] ) 3. The package structure of claim 1, wherein the differential coupling bus further comprises a non-galvanic connection between the differential transmission lines and at least one of the first quantum bit chip and the second quantum bit chip. The first qubit 240 and the second qubit (not shown in FIG. 3) are coupled differentially by the coupled-line bus 220. [ Solgun para 0041] Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 2 , 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Solgun and further in view of Yohannes et al., US Patent Application (20220237495) , hereinafter “ Yohannes ” . Regarding claim 2 Solgun teaches claim 1 in addition Solgun does not each but Yohannes teaches wherein the differential coupling bus further comprises galvanic connections between the differential transmission lines and at least one of the first quantum bit chip and the second quantum bit chip. providing galvanic connection between the grounds on both chips 102 and 104 to form a common ground between them; (5) Providing galvanic connections of signal lines to form superconducting lossless loops between the chips 102 and 104 [Yohannes para 0046] Solgun discloses a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission. Yohannes discloses combine quantum computing, classical qubit control/readout, and classical digital computing in a scalable computing system based on superconducting qubits and special interconnection designs for connecting hardware components within a multi-stage cryogenic system to provide fast communications between the quantum computing module and its controller while allowing efficient management of wiring with other modules Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Solgun and Yohannes in the art of a quantum computing , as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Yohannes i mproves Solgun ’s systems, methods and/or apparatus by us ing direct bump-bonding which ha ve a number of advantages and serves to e stablishing mechanical connection between the quantum chip and the classical controller chip which m inimiz es the noise influence to the quantum chip and to minimiz e the communication time between the classical controller chip and the quantum chip . Regarding claim 4 Solgun teaches claim 3 in addition Solgun does not each but Yohannes teaches wherein: the non-galvanic connection comprises a differential coupling capacitor connected to the differential transmission lines; and the differential coupling capacitor is aligned to superconducting pads of a first quantum bit on the first quantum bit chip to implement a vacuum gap capacitor which provides the non-galvanic connection. the quantum qubit chip 102 is capacitively coupled to a corresponding readout resonator in the classical chip 104, where the coupling takes place between the two capacitor pads [Yohannes para 00 57 ] mechanically and electrically, as a multichip module via superconducting bumps, capacitive coupling, or magnetic coupling via vacuum to transfer control signals and readout signals therebetween [Yohannes para 0023] Regarding claim 5 Solgun teaches claim 1 in addition Solgun does not each but Yohannes teaches wherein the differential coupling bus comprises a tunable coupler that is configured to control interactions between a first quantum bit on the first quantum bit chip and a second quantum bit on the second quantum bit chip. the coupling between the qubit and the readout resonator are via capacitive or inductive coupling … Two bias currents from current sources I.sub.B1 and I.sub.B2 are used to tune the phases of the two comparator junctions. [Yohannes para 0059] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ROBERT J MICHAUD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3981 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 8:30 - 5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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