Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
I. CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/2025 has been entered.
RESPONSE TO AMENDMENT
Acknowledgment is made of the amendment filed 10/21/2025, in which:claims 1, 7, 11, 15, and 20 are amended; claims 8, 10, 12, 14, 18-19, 22-24, and 28-30 are cancelled; and the rejections of the claims are traversed. Claims 1-7, 9, 11, 13, 15-17, 20-21, and 25-27 are currently pending and an Office Action on the merits follows.
ALLOWABLE SUBJECT MATTER
Claim 6 and 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 6 is objected to because the cited references do not disclose “wherein a pixel circuit arranged in each of the sub-pixels of the first color, the second color, and the third color is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period; a voltage of the first gate signal is a gate-on voltage during the initialization period, the sensing period, and the emission period, is a gate-off voltage during the anode reset period, and is the gate-on voltage or the gate-off voltage during the data writing period; a voltage of the second gate signal is the gate-on voltage during the initialization period, the anode reset period, and the emission period, and is the gate-off voltage during the sensing period and the data writing period; a voltage of the third gate signal is the gate-on voltage during the data writing period, and is the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the emission period; a voltage of the fourth gate signal is the gate-on voltage during the initialization period and the sensing period, and is the gate-off voltage during the data writing period, the anode reset period, and the emission period; a voltage of the fifth gate signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and is the gate-off voltage during the emission period; and each of the first to fifth switch elements is turned on based on the gate-on voltage, and turned off based on the gate-off voltage“.
Claim 25-27 are objected to because the cited references do not disclose “ wherein the pixel circuit is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period; a voltage of the first emission control signal is a gate-on voltage during the initialization period, the sensing period, and the emission period, is a gate-off voltage during the anode reset period, and is the gate-on voltage or the gate-off voltage during the data writing period; a voltage of the second emission control signal is the gate-on voltage during the initialization period, the anode reset period, and the emission period, and is the gate-off voltage during the sensing period and the data writing period; a voltage of the first scan signal is the gate-on voltage during the data writing period, and is the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the emission period; a voltage of the second scan signal is the gate-on voltage during the initialization period and the sensing period, and is the gate-off voltage during the data writing period, the anode reset period, and the emission period; a voltage of the third scan signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and is the gate-off voltage during the emission period; and each of the first to fifth switch elements is turned on based on the gate-on voltage and turned off based on the gate-off voltage” and “wherein the pixel circuit is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period; during the initialization period, the initialization voltage is applied to the second node and the reference voltage is applied to the third node; during the sensing period, a threshold voltage of the driving element is stored in the first capacitor; during the data writing period, the data voltage is applied to the second node; during the anode reset period, the reference voltage is applied to the third node and the fourth node; and during a boosting period of the emission period, the second switch element is turned on so that the third node and the fourth node are electrically connected to each other, and wherein the light emitting element emits light in accordance with a current from the driving element after the boosting period”.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-5, 7, 9, 11, 13, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. US 20240206229 in view of Lai et al. US 20220335897.
Consider claim 1. Min discloses a display panel fig. 1 10, comprising:
a sub-pixel of a first color [0058] red;
a sub-pixel of a second color [0058] green; and
a sub-pixel of a third color [0058] blue, wherein each of the sub-pixels of the first color, the second color, and the third color includes [0058] red green and blue or white subpixels:
a driving element fig. 3 driving transistor T1 including a first electrode electrically connected to a first node, a gate electrode electrically connected to a second node, and a second electrode electrically connected to a third node see fig. 3 T1 is connected to node between T1 T5 and nodes N1 and N2; and
a light emitting element including an anode electrode connected to the third node and configured to be driven by a current from the driving element see fig. 3 OLED connected to N2 and driven by current of T1;
a first capacitor fig. 3 Cst electrically connected between the second node and the third node see fig. 1 Cst connected between N1 and N2; and
a second capacitor fig. 2 Chold electrically connected to the third node see fig. 3 Chold connected between ELVDD and N2 , wherein the second capacitor has a different capacitance for each of the sub-pixels of the first color, the second color, and the third color see fig. 11 sizes of Chold for SP1 SP2 SP3 are different [0152-0153].
the sub-pixel of the first color includes a second-first capacitor see Min fig. 11 Chold in SP1;
the sub-pixel of the second color includes a second-second capacitor see Min fig. 11 Chold in SP2;
the sub-pixel of the third color includes a second-third capacitor see Min fig. 11 Chold in SP3;
wherein a capacitance of a capacitor of the light emitting element is increased in an order from larger to smaller of the sub-pixel of the third color, the sub-pixel of the second color, and the sub-pixel of the first color Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153]. Thus, the capacitance of the sub-pixel of the third color > capacitance of the sub-pixel of the second color > capacitance of the sub-pixel of the first color, as explained paragraph 0098 below.
Note: [0098] of the Application’s specification states the following: the capacitance of the second-third capacitor Ca3 is larger than that of the second-first capacitor Ca1 and second-second capacitor Ca2, and the capacitance of the second-second capacitor Ca2 is larger than that of the second-first capacitor Ca1. In other words, the capacitance of the second-first capacitors Ca1, second-second capacitor Ca2, and second-third capacitor Ca3 is increased in the order from larger to smaller of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R.
Min does not disclose a light emitting element connected to a fourth node and a second capacitor connected between the third node and the fourth node. a second switch element including a first electrode electrically connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode electrically connected to the fourth node. second capacitor electrically connected in parallel with the second switch element
Lai however discloses light emitting element connected to a fourth node fig. 4 fig. 11 18 is connected to a node which connected to drain of M3 and a second capacitor connected between the third node and the fourth node see fig. 4 and fig. 11 C2 is connected between third node which is between M1 and M3 and fourth node which is between M3 and 18. a second switch element including a first electrode electrically connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode electrically connected to the fourth node see Lai fig. 4 fig. 11 M3 gate driven by signal Emit, source connected to third node and drain connected fourth node. second capacitor electrically connected in parallel with the second switch element Lai fig. 4 fig. 11 C2 is in parallel with M3 between third and fourth node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel circuit of Min to include a light emitting element connected to a fourth node and a second capacitor connected between the third node and the fourth node. a second switch element including a first electrode electrically connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode electrically connected to the fourth node. second capacitor electrically connected in parallel with the second switch element, as taught by Lai, to improve compensation effect thereby improving a uniformity of the display luminance of the entire display panel and reducing luminance deviation [0043].
Consider claim 2. Min as modified Lai discloses display panel of claim 1, wherein each of the sub-pixels of the first color, the second color, and the third color further includes:
a first switch element including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a second electrode electrically connected to the first node see Min fig. 3 T5 gate driven by signal EM source driven by ELVDD and drain connected to first node; and
the sub-pixel of the first color includes a second-first capacitor see Min fig. 11 Chold in SP1;
the sub-pixel of the second color includes a second-second capacitor see Min fig. 11 Chold in SP2;
the sub-pixel of the third color includes a second-third capacitor see Min fig. 11 Chold in SP3;
the first color is red, the second color is green, and the third color is blue Min [0058] Red Green and Blue;
a capacitance of the second-third capacitor is larger than a capacitance of each of the second-first capacitor and second-second capacitor see Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153]; and
the capacitance of the second-second capacitor is larger than the capacitance of the second-first capacitor see Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153].
Motivation to combine is similar to motivation in claim 1.
Consider claim 3. Min as modified by Lai disclose the display panel of claim 2, further comprising:
a pattern of a first metal layer disposed on a first insulating layer and electrically connected to the sub-pixels of the first color, the second color, and the third color Min fig. 3-4 fig. 10 the insulating layer 111, fig. 11 shows the patter of the metal layer of the capacitors CE4 ;
a second insulating layer configured to cover the pattern of the first metal layer and the first insulating layer Min fig. 3-4 fig. 10 the insulating layer 113 covers CE4, fig. 11 shows the pattern of the metal layer of the capacitors CE4 and CE3;
patterns of a second metal layer disposed on the second insulating layer Min fig. 3-4 fig. 10 covers electrode CE3 is on the insulating layer 113, fig. 11, the patterns being arranged on the sub-pixels of the first color, the second color, and the third color and separated among the sub-pixels Min fig. 4 fig. 11 SP1 SP2 SP3; and
a third insulating layer configured to cover the patterns of the second metal layer and the second insulating layer Min fig. 3-4 fig. 10 the insulating layer 115 covers CE3, wherein the patterns of the second metal layer includes: a second-first capacitor electrode disposed in the sub-pixel of the first color; a second-second capacitor electrode disposed in the sub-pixel of the second color a second-third capacitor electrode disposed in the sub-pixel of the third color Min fig. 11 shows the pattern of the metal layer of the capacitors CE4 and CE3 for SP1 SP2 and SP3 and,
wherein the second-third capacitor electrode is larger than each of the second-first capacitor electrode and second-second capacitor electrode in size; and the second-second capacitor electrode is larger than the second-first capacitor electrode in size see Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153].
Consider claim 4. Min as modified by Lai disclose the display panel of claim 2, wherein a constant voltage applied to the second-first capacitor, the second-second capacitor and the second-third capacitor is either equal to or different from the pixel driving voltage Min fig. 3-4 ELVDD is applied to Chold.
Consider claim 5. Min as modified by Lai disclose the display panel of claim 2, wherein each of the sub-pixels of the first color, the second color, and the third color further includes:
a third switch element including a first electrode electrically connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T2 gate driven by signal GW source connected to data line DL and drain connected to node N1; and
a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T4 gate driven by signal GI, source connected to Vint and drain connected to node N1; and
a fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode electrically connected to the fourth node see Lai fig. 4 fig. 11 M5 gate driven by signal S2 source connected to Var signal and drain connected to node between M3 and EL 18,
and wherein the first capacitors in the sub-pixels of the first color, the second color, and the third color have a same capacitance See Min fig. 11 Cst of SP1 SP2 SP3 are all the same size.
Motivation to combine is similar to motivation in claim 1.
Claim 7 is rejected for similar reasons to claim 2 except where the capacitance of the second-second capacitor is larger than the capacitance of the second-third capacitor which is disclosed in Min [0153] a capacitance of the 1-2.sup.th capacitor may be less than a capacitance of the 2-2.sup.th capacitor, and a capacitance of the 2-2.sup.th capacitor may be less than a capacitance of the 3-2.sup.th capacitor. However, the present disclosure is not limited thereto, and various modifications may be made as needed or desired. For example, a capacitance of the 1-2.sup.th capacitor may be greater than a capacitance of the 2-2.sup.th capacitor, and a capacitance of the 2-2.sup.th capacitor may be greater than a capacitance of the 3-2.sup.th capacitor.
Claim 9 is rejected for similar reasons to claim 4.
Claim 11 is rejected for similar reasons to claim 2 except where a second-second capacitor; the sub-pixel of the third color includes a second-third capacitor; a pixel driving voltage is applied to the first node; the anode electrode of the light emitting element is electrically connected to the third node; the first color is red, the second color is green, and the third color is blue; which is disclosed in Min [0153] a capacitance of the 1-2.sup.th capacitor may be less than a capacitance of the 2-2.sup.th capacitor, and a capacitance of the 2-2.sup.th capacitor may be less than a capacitance of the 3-2.sup.th capacitor. However, the present disclosure is not limited thereto, and various modifications may be made as needed or desired. For example, a capacitance of the 1-2.sup.th capacitor may be greater than a capacitance of the 2-2.sup.th capacitor, and a capacitance of the 2-2.sup.th capacitor may be greater than a capacitance of the 3-2.sup.th capacitor.
Claim 13 is rejected for similar reasons to claim 4.
Consider claim 20. Min discloses a pixel circuit fig. 3 pixel circuit comprising:
a driving element fig. 3 driving transistor T1 including: a first electrode electrically connected to a first node, a gate electrode electrically connected to a second node, and a second electrode electrically connected to a third node; see fig. 3 T1 is connected to node between T1 T5 and nodes N1 and N2; and
a light emitting element adjacent to the driving element, the light emitting element including: third node, and a cathode electrode to which a cathode voltage is applied see fig. 3 OLED connected to N2 and ELVSS;
a first capacitor electrically connected between the second node and the third node fig. 3 Cst
Min does not disclose a fourth node and a second switch element including: a first electrode electrically connected to the third node, a gate electrode to which a second emission control signal is applied, and a second electrode electrically connected to the fourth node see Lai fig. 4 fig. 11 M3 gate driven by signal Emit, source connected to third node and drain connected fourth node, the second switch element configured to electrically connect the third node to the fourth node based on a gate-on voltage of the second emission control signal see Lai fig. 4 fig. 11 M3 is turned on by signal Emit which connects third and fourth node ; and
a second capacitor electrically connected between the third node and the fourth node Lai fig. 4 fig. 11 C2.
wherein the pixel circuit is included in a sub-pixel of a first color [0058] red, a sub-pixel of a second color [0058] green, and a sub-pixel of a third color [0058] blue
wherein the second capacitor has a different capacitance for each of the sub-pixels of the first color, the second color and the third color see fig. 11 sizes of Chold for SP1 SP2 SP3 are different [0152-0153].
wherein the sub-pixel of the first color includes a second-first capacitor see Min fig. 11 Chold in SP1;
wherein the sub-pixel of the second color includes a second-second capacitor see Min fig. 11 Chold in SP2;
wherein the sub-pixel of the third color includes a second-third capacitor see Min fig. 11 Chold in SP3;
wherein a capacitance of a capacitor of the light emitting element is increased in an order from larger to smaller of the sub-pixel of the third color, the sub-pixel of the second color, and the sub-pixel of the first color Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153]. Thus, the capacitance of the sub-pixel of the third color > capacitance of the sub-pixel of the second color > capacitance of the sub-pixel of the first color, as explained paragraph 0098 below.
Note: [0098] of the Application’s specification states the following: the capacitance of the second-third capacitor Ca3 is larger than that of the second-first capacitor Ca1 and second-second capacitor Ca2, and the capacitance of the second-second capacitor Ca2 is larger than that of the second-first capacitor Ca1. In other words, the capacitance of the second-first capacitors Ca1, second-second capacitor Ca2, and second-third capacitor Ca3 is increased in the order from larger to smaller of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R.
wherein a capacitance of the second capacitor is different for each pixel of different colors Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153].
Min does not disclose a fourth node and a second switch element including: a first electrode electrically connected to the third node, a gate electrode to which a second emission control signal is applied, and a second electrode electrically connected to the fourth node, the second switch element configured to electrically connect the third node to the fourth node based on a gate-on voltage of the second emission control signal and a second capacitor electrically connected in parallel with the second switch element
Lai however discloses light emitting element with a fourth node fig. 4 fig. 11 18 is connected to a node which is between M3 and 18 and a second switch element including: a first electrode electrically connected to the third node, a gate electrode to which a second emission control signal is applied, and a second electrode electrically connected to the fourth node see Lai fig. 4 fig. 11 M3 gate driven by signal Emit, source connected to third node and drain connected fourth node, the second switch element configured to electrically connect the third node to the fourth node based on a gate-on voltage of the second emission control signal and a second capacitor electrically connected in parallel with the second switch element Lai fig. 4 fig. 11 C2 is in parallel with M3 between the third and fourth node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel circuit of Min to a fourth node and a second switch element including: a first electrode electrically connected to the third node, a gate electrode to which a second emission control signal is applied, and a second electrode electrically connected to the fourth node, the second switch element configured to electrically connect the third node to the fourth node based on a gate-on voltage of the second emission control signal and a second capacitor electrically connected in parallel with the second switch element, as taught by Lai, to improve compensation effect thereby improving a uniformity of the display luminance of the entire display panel and reducing luminance deviation [0043].
Consider claim 21. Min as modified by Lai discloses pixel circuit of claim 20, further comprising:
a first switch element including: a first electrode electrically connected to a constant voltage line to which a pixel driving voltage is applied, a gate electrode to which a first emission control signal is applied, and a second electrode electrically connected to the first node see Min fig. 3 T5 gate driven by signal EM source driven by ELVDD and drain connected to first node , the first switch element configured to electrically connect the constant voltage line to the first node based on a gate-on voltage of the first emission control signal fig. 3 when EM turns on T5 then the ELVDD is applied to the first node which is between T5 and T1;
a third switch element including: a first electrode to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T2 gate driven by signal GW source connected to data line DL and drain connected to node N1, the third switch element configured to supply the data voltage to the second node based on a gate-on voltage of the first scan signal see Min fig 3 when T2 is turned on a data voltage is applied to the node N1;
a fourth switch element including: a first electrode to which an initialization voltage is applied, a gate electrode to which a second scan signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T4 or T3 gate driven by signal GI or GR, source connected to Vint Vref and drain connected to node N1, the fourth switch element configured to supply the initialization voltage to the second node based on a gate-on voltage of the second scan signal Min fig. 3 when T4 or T3 is turned on via GI or GR then Vint or Vref is applied to N1;
a fifth switch element including: a first electrode electrically connected to the fourth node, a gate electrode to which a third scan signal is applied, and a second electrode to which a reference voltage is applied see fig. 4 fig. 11 M5 gate driven by signal S2 source connected to Var signal and drain connected to node between M3 and EL 18, the fifth switch element configured to supply the reference voltage to the fourth node based on a gate-on voltage of the third scan signal fig. 4 fig. 11 when gate signal S2 is applied the Var signal is applied to the fourth node;
Motivation to combine is similar to motivation in claim 20.
2. Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. US 20240206229 in view of Lai et al. US 20220335897 and further in view of Kim et al. US 20170329189.
Consider claim 15. Min as modified by Lai discloses all features of claim 15 (as shown in rejection of claim 1 above) but do not explicitly illustrate a display panel having a plurality of data lines, a plurality of gate lines, a plurality of power line; a data driver configured to output a data voltage of pixel data to the plurality of data lines; and a gate driver configured to sequentially supply gate signals to the plurality of gate lines,
Kim however discloses display panel having a plurality of data lines fig. 1 see plurality of data lines DL, a plurality of gate lines fig. 1 see plurality of Gate lines GL, a plurality of power line fig. 1 see plurality of power lines e.g. lines carrying VDD VSS Vinit; a data driver configured to output a data voltage of pixel data to the plurality of data lines fig. 1 see data driver DD supplying pixel with Vdata via data lines DL; and a gate driver configured to sequentially supply gate signals to the plurality of gate lines fig. 1 [0088] see gate driver GD supplying pixel with scan signals via gate lines GL sequentially.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel circuit of Min to include display panel having a plurality of data lines, a plurality of gate lines, a plurality of power line; a data driver configured to output a data voltage of pixel data to the plurality of data lines; and a gate driver configured to sequentially supply gate signals to the plurality of gate lines, as taught by Kim, in order to perform the basic operation of the display device which is display images via driving the pixel circuit fig. 1 [0092].
Consider claim 16. Min as modified by Lai and Kim disclose the display device of claim 15, wherein each of the sub-pixels further includes:
a first switch element including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a second electrode electrically connected to the first node see Min fig. 3 T5 gate driven by signal EM source driven by ELVDD and drain connected to first node;
a third switch element including a first electrode electrically connected to the data line to which the data voltage of the pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T2 gate driven by signal GW source connected to data line DL and drain connected to node N1;
a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode electrically connected to the second node see Min fig. 3 T4 gate driven by signal GI, source connected to Vint and drain connected to node N1; and
a fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode electrically connected to the fourth node see Lai fig. 4 fig. 11 M5 gate driven by signal S2 source connected to Var signal and drain connected to node between M3 and EL 18, and wherein:
the constant voltage applied to the second capacitor is equal to or different from the pixel driving voltage Min fig. 3-4 ELVDD is applied to Chold;
a capacitance of the first capacitors in the red sub-pixels, the green sub-pixels, and the blue sub-pixels is the same See Min fig. 11 Cst of SP1 SP2 SP3 are all the same size;
the capacitance of the second capacitors in the plurality of blue sub-pixels is larger than the capacitance of each of the second capacitors in the plurality of red and the plurality of green sub-pixels; and the capacitance of the second capacitors in the plurality of green sub-pixels is larger than the capacitance of the second capacitors in the plurality of red sub-pixels see Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153].
Motivation to combine is similar to motivation in claim 16.
Consider claim 17. Min as modified by Lai and Kim disclose the display device of claim 16, wherein the display panel further includes:
a pattern of a first metal layer disposed on a first insulating layer and electrically connected to the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels Min fig. 3-4 fig. 10 the insulating layer 111, fig. 11 shows the patter of the metal layer of the capacitors CE4 [0058] red green blue;
a second insulating layer configured to cover the pattern of the first metal layer and the first insulating layer Min fig. 3-4 fig. 10 the insulating layer 113 covers CE4, fig. 11 shows the pattern of the metal layer of the capacitors CE4 and CE3;
patterns of a second metal layer disposed on the second insulating layer Min fig. 3-4 fig. 10 covers electrode CE3 is on the insulating layer 113, fig. 11, the patterns being disposed on the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels and being separated between neighboring sub-pixels Min fig. 4 fig. 11 SP1 SP2 SP3;
a third insulating layer configured to cover the patterns of the second metal layer and the second insulating layer Min fig. 3-4 fig. 10 the insulating layer 115 covers CE3, wherein the patterns of the second metal layer includes: a second-first capacitor electrode disposed in the plurality of red sub-pixels; a second-second capacitor electrode disposed in the plurality of green sub-pixels; and a second-third capacitor electrode disposed in the plurality of blue sub-pixels Min fig. 11 shows the pattern of the metal layer of the capacitors CE4 and CE3 for SP1 SP2 and SP3 and,
wherein the second-third capacitor electrode is larger than each of the second-first capacitor electrode and the second-second capacitor electrode in size; and the second-second capacitor electrode is larger than the second-first capacitor electrode in size see Min fig. 11 Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153].
RESPONSE TO ARGUMENTS
Applicant's arguments with have been fully considered but are moot in view of the new grounds of rejection.
The Applicant’s remarks (pages 14-15) indicate that the cited references do not discloses “wherein a capacitance of a capacitor of the light emitting element is increased in an order from larger to smaller of the sub-pixel of the third color, the sub-pixel of the second color, and the sub-pixel of the first color”.
The Office respectfully disagrees. The Applicant’s specification [0098] clarifies the language “the capacitance of the second-third capacitor Ca3 is larger than that of the second-first capacitor Ca1 and second-second capacitor Ca2, and the capacitance of the second-second capacitor Ca2 is larger than that of the second-first capacitor Ca1” with “the capacitance of the second-first capacitors Ca1, second-second capacitor Ca2, and second-third capacitor Ca3 is increased in the order from larger to smaller of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R”. Since Min explicitly teaches (see fig. 11) Chold in SP3 > Chold in SP2> Chold in SP1 [0152-0153], Min therefore also teaches the capacitance of the second-first capacitors Ca1, second-second capacitor Ca2, and second-third capacitor Ca3 is increased in the order from larger to smaller of the blue sub-pixel B, the green sub-pixel G, and the red sub-pixel R, as per the passage in [0098] of the Applicant’s specification.
For at least these reasons the cited references still read on the claimed invention.
VI. CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. US 20200111413 discloses a pixel circuit of an OLED device with subpixels with different capacitor sizes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on 5712727671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2621
/IBRAHIM A KHAN/ 12/12/2025Primary Examiner, Art Unit 2621