Prosecution Insights
Last updated: October 02, 2026
Application No. 18/539,490

ELECTROMAGNETIC WAVE CALCULATION SYSTEM AND METHOD OF OBTAINING PREVIOUS DATA

Final Rejection §103
Filed
Dec 14, 2023
Priority
Feb 14, 2023 — JP 2023-020404
Examiner
TCHATCHOUANG, CARL F.R.
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
149 granted / 180 resolved
+14.8% vs TC avg
Moderate +15% lift
Without
With
+14.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
29 currently pending
Career history
207
Total Applications
across all art units

Statute-Specific Performance

§101
30.1%
-9.9% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
7.2%
-32.8% vs TC avg
§112
21.9%
-18.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 180 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Claims 1-23 are pending Claims 1, 15-18 has been amended Response to Arguments Applicant’s arguments, see pages 8-12, filed 6/12/2026, with respect to the rejection(s) of claim(s) 1-23 under U.S.C. 101 and 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over KUNITAKE; Hitoshi et al. (US 20220035980 A1; hereinafter Kunitake; provided by the applicant) in view of LI; Jia et al. (US 20200386807 A1; hereinafter Li; provided by the applicant). Regarding claim 1, Kunitake teaches An electromagnetic wave calculation system (par.17 teaches computer as EM wave calculation system) calculating an electromagnetic wave (par.117-119 teach calculating an electromagnetic wave) generated in a semiconductor device (transistors 150 A-D), comprising: an electromagnetic wave simulator (par.117-119 and figs 9 show an EM wave simulator); and a previous data memory (Par.92 and 103 teach rewritable memory as previous data memory), wherein the electromagnetic wave simulator and the previous data memory have communication (par.91, 97 and 102 teach communication) with each other via a network (par.99 teaches network), the previous data memory records electromagnetic wave data of the semiconductor device corresponding to a type name of the semiconductor device (par.53 teaches type name semiconductor MIS; par.107 further teaches transistor compact models) and a usage condition of the semiconductor device (par.68 teaches CV characteristics as usage condition) as previous data, and when the type name and the usage condition of the semiconductor device are inputted (par.107 teaches input of type and usage condition through model generated through user instructions) , the electromagnetic wave simulator has communication with the previous data memory (par.97 teaches data input from memory). Kunitake fails to teach and outputs, as a prediction of the semiconductor device operating under a similar usage condition, the electromagnetic wave data under the usage condition of the semiconductor device. Li further teaches outputs, as a prediction of the semiconductor device operating under a similar usage condition, the electromagnetic wave data under the usage condition of the semiconductor device (par.62 teaches outputting a prediction of similar usage condition as the output recognition results). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kunitake to include the teachings of Li; which would provide arrangements and techniques for augmented-reality-based testing modification which would cut costs and time delays as disclosed by Li (par.3-4). Regarding claim 2, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 1, Kunitake further teaches wherein the electromagnetic wave simulator is built up on a computer connected to the network (par.99). Regarding claim 3, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 1, Kunitake further teaches wherein the electromagnetic wave simulator is accessed from a homepage of a company of a user of the semiconductor device (par.99 teaches the world wide web which can be used to access the EM wave simulator from a homepage of a company of a user of the semiconductor device.). Regarding claim 4, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 1, Kunitake further teaches wherein the semiconductor device includes a transistor (par.58 teaches transistor in semiconductor), and stored in the previous data memory is profile data of electromagnetic wave strength at a time switching-operating the transistor under the usage condition for each the type name of the semiconductor device (par.105 “the simulation device 200 can reproduce operation characteristics similar to those of an actual device by using a generated device model.” Teaches profile stored at a time switching-operating). Regarding claim 5, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 4, Kunitake further teaches wherein the usage condition includes a voltage value applied to the semiconductor device (par 116-117), a current value of current flowing in the semiconductor device (par 116-117), and a carrier frequency as a total number of switching of the transistor. Regarding claim 7, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 4, Kunitake further teaches wherein the usage condition includes a dead time as an interval period between pulses of a pulse signal for turning on and off the transistor (fig.11a-c teaches dead time as gap between gaps). Regarding claim 8, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 4, Li further teaches wherein the usage condition includes an output frequency of the semiconductor device (par.66 and fig.4 teach outputting component data, which could be frequency component data). Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kunitake in view of Li further in view of FUJITA; Miwako et al. (US publication #US 20200217884 A1; provided by the applicant; hereinafter Fujita; previously cited). Regarding claim 6, Kunitake in view of Li teaches the electromagnetic wave calculation system according to claim 4, but fails to teach wherein the usage condition includes a length and inductance of a bus wiring connected to the transistor from a smoothing capacitor connected to the semiconductor device. Fujita does teach wherein the usage condition includes a length and inductance (par.159 “par.159 “the shape, dimension, and material of wirings (wires, lead flames and the like) bonded to surface electrodes formed on the semiconductor device”) of a bus wiring connected to the transistor from a smoothing capacitor connected to the semiconductor device (fig.3 shows a bus wiring connected to the transistor from a smoothing capacitor connected to the semiconductor device.). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kunitake in view of Li to include the teachings of Fujita; which would provide an improved estimation method of estimating the electromagnetic noise of an apparatus by acquiring a plurality of evaluation benchmarks for the semiconductor device that are output in correspondence with the switching operation under a plurality of conditions as disclosed by Fujita(par.19). Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 9, the prior art does not teach or suggest, in combination with the rest of the limitation of claim 9, “… wherein a measured object including the semiconductor device is prepared, and the previous data detects the electromagnetic wave generated by switching-operating the transistor constituting the measured object under the usage condition with an antenna to be a voltage signal, and is profile data of a voltage signal after Fourier transformation in which the voltage signal is cut with a predetermined temporal width and is partially Fourier transformed to convert into frequency.” Claims 10-23 would also be allowable due to their dependence on claim 9. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. US 10670639 B2; Nakajima; Nozomu is an Apparatus for detecting alternating current zero cross and voltage. US 20020037596 A1; Yamaguchi, Tetsuya is a Simulator of semiconductor device circuit characteristic and simulation method. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARL F.R. TCHATCHOUANG whose telephone number is (571)272-3991. The examiner can normally be reached Monday - Friday 8:00am -5:00am. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CARL F.R. TCHATCHOUANG/Examiner, Art Unit 2858 /HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Show 2 earlier events
May 21, 2026
Interview Requested
May 27, 2026
Examiner Interview Summary
May 27, 2026
Applicant Interview (Telephonic)
Jun 12, 2026
Response Filed
Jul 22, 2026
Final Rejection mailed — §103
Sep 16, 2026
Interview Requested
Sep 23, 2026
Applicant Interview (Telephonic)
Sep 23, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
98%
With Interview (+14.7%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 180 resolved cases by this examiner. Grant probability derived from career allowance rate.

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