DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Package Including a Lower Package, an Upper Package, and an Expanded Structure.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7, 10, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (US 11942435).
Regarding Claim 1, Wang et al discloses a semiconductor package (package structure 500 [column 15, lines 30-37] Fig 26) comprising:
a first wiring structure (front-side redistribution structure 131 [column 6, lines 15-35]);
a second wiring structure (back-side redistribution structure 110 [column 5, lines 60-67]) on the first wiring structure (131);
a semiconductor chip (semiconductor substrate 118 [column 5, lines 13-33]) between the first wiring structure (131) and the second wiring structure (110); and
an expanded structure (structure that contains through vias 112 [column 6, lines 6-15]) that electrically connects the first wiring structure (131) with the second wiring structure (110) and surrounds the semiconductor chip (118),
wherein at least one of the first wiring structure (131) and the second wiring structure (110) includes a first insulating layer (lower portion of dielectric layer 108, which may be polyimide, [column 3, lines 60-67] shown in annotated Fig 26) on the semiconductor chip (118) and the expanded structure (structure that contains through vias 112),
a first wiring layer (metallization pattern 106 [column 3, lines 60-67]) on the first insulating layer (lower portion of 108 shown in annotated Fig 26),
a second insulating layer (top portion of 108 shown in annotated Fig 26) covering the first insulating layer (lower portion of 108 shown in annotated Fig 26) and the first wiring layer (106),
a crack prevention layer (dielectric layer 104, which may be silicon oxide or silicon nitride [column 3, lines 18-33]) on the second insulating layer (top portion of 108 shown in annotated Fig 26), and
a second wiring layer (functional connectors 314 [column 14, lines 25-38]) on the second insulating layer (top portion of 108 shown in annotated Fig 26) and the crack prevention layer (104),
the second wiring layer (314) includes a pad portion (shown in annotated Fig 26),
the crack prevention layer (104) overlaps the pad portion (shown in annotated Fig 26) in a vertical direction (vertical y direction) and extends from an edge of the pad portion (shown in annotated Fig 26) in a horizontal direction (horizontal x direction shown in cross-section Fig 26) in a plan view (would extend in the plan view in the horizontal x direction shown in the cross-section Fig 26), and
the crack prevention layer (104) is apart from the first wiring layer (106) in the vertical direction (vertical y direction) with a portion of the second insulating layer (top portion of 108 shown in annotated Fig 26) therebetween.
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Regarding Claim 2, Wang et al discloses the limitations of claim 1 as explained above. Wang et al further discloses
wherein the crack prevention layer (104 Fig 26) completely covers an upper surface of the second insulating layer (upper portion of 108 shown above in annotated Fig 26).
Regarding Claim 4, Wang et al discloses the limitations of claim 1 as explained above. Wang et al further discloses
wherein a thickness of the crack prevention layer (104) is equal to or greater than a thickness of the first wiring layer (106) (shown in annotated Fig 26).
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Regarding Claim 5, Wang et al discloses the limitations of claim 4 as explained above. Wang et al further discloses
wherein the portion of the second insulating layer (upper portion of 108 shown above in annotated Fig 26) between the crack prevention layer (104 Fig 26) and the first wiring layer (106 Fig 26) has a thickness smaller (shown in annotated Fig 26) than each of a thickness of the first wiring layer (106 Fig 26) and a thickness of the crack prevention layer (104 Fig 26).
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Regarding Claim 7, Wang et al discloses the limitations of claim 1 as explained above. Wang et al further discloses
wherein each of the first insulating layer (lower portion of 108 shown above in annotated Fig 26) and the second insulating layer (upper portion of 108 shown above in annotated Fig 26) comprises an organic material (polyimide, [column 3, lines 60-67] which is organic), and
the crack prevention layer (104 Fig 26) comprises an inorganic material (104, which may be silicon oxide or silicon nitride [column 3, lines 18-33] which is an inorganic material) having a fracture toughness higher than a fracture toughness of the first insulating layer (lower portion of 108 shown above in annotated Fig 26) and a fracture toughness of the second insulating layer (upper portion of 108 shown above in annotated Fig 26) (the examiner notes that since the material of the crack prevention layer 104 is the same as the material of the crack prevention layer of the instant application, and the material of the second redistribution insulating layers 108 is the same as in the instant application, the reference Wang et al is considered to meet this limitation).
Regarding Claim 10, Wang et al discloses the limitations of claim 1 as explained above. Wang et al further discloses
wherein at least one of the first wiring structure (front-side redistribution structure 131 [column 6, lines 15-35] Fig 26) and the second wiring structure (back-side redistribution structure 110 [column 5, lines 60-67]) further comprises a redistribution via (upper portion of 112, Fig 26), and
the redistribution via (upper portion of 112, Fig 26) electrically connects the second wiring layer (functional connectors 314 [column 14, lines 25-38]) with the first wiring layer (metallization pattern 106 [column 3, lines 60-67]) through the crack prevention layer (104 Fig 26) and the second insulating layer (upper portion of 108 shown above in annotated Fig 26).
Regarding Claim 18, Wang et al discloses a semiconductor package (package structure 500 [column 15, lines 30-37] Fig 26) comprising:
a lower package (first package 200 [column 12, lines 43-67] Fig 26) including a first wiring structure (front-side redistribution structure 131 [column 6, lines 15-35] Fig 26) including a plurality of first redistribution patterns (metallization patterns 142, 156 [column 8, lines 45-60], 170 [column 9, lines 45-55] Fig 20A) and a plurality of first redistribution insulating layers (dielectric layers 133, 146 [column 8, lines 40-55], 160, 174 [column 9, lines 60-67] Fig 20A) surrounding the plurality of first redistribution patterns (142, 156, 170 Fig 20A),
a second wiring structure (back-side redistribution structure 110 [column 5, lines 60-67], bond pads 304 [column 13, lines 45-60], through vias 306 [column 13, lines 45-60] and functional connectors 314 [column 14, lines 25-38] Fig 26) on the first wiring structure (131 Fig 26),
the second wiring structure (110, 304, 306, 314 Fig 26) including a plurality of second redistribution patterns (metallization pattern 106 [column 3, lines 60-67] Fig 20A, bonding pads 304, through vias 306, and functional connectors 314 Fig 26), a plurality of second redistribution insulating layers (lower portion of 108, upper portion of 108 [column 3, lines 60-67] Fig 20A, shown in annotated Fig 26) surrounding the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26), a crack prevention layer (dielectric layer 104, which may be silicon oxide or silicon nitride [column 3, lines 18-33]), and a plurality of upper surface connection pad layers (main portion of functional connectors 314 [column 14, lines 25-38] shown in annotated Fig 26);
a semiconductor chip (semiconductor substrate 118 [column 5, lines 13-33] Fig 26) between the first wiring structure (131 Fig 26) and the second wiring structure (110, 304, 306, and 314 Fig 26); and
an expanded structure (structure that contains through vias 112 [column 6, lines 6-15] Fig 26) that electrically connects the plurality of first redistribution patterns (142, 156, 170 Fig 20A) with the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26) and surrounds the semiconductor chip (118 Fig 26),
an upper package (second package 300 [column 12, lines 43-67] Fig 26) on the lower package (200 Fig 26), the upper package (300 Fig 26) including an auxiliary semiconductor chip (stacked dies 308A and 308B [column 12, lines 43-67] Fig 26); and
a plurality of package connection terminals (bond pads 304 shown in annotated Fig 26) attached to the plurality of upper surface connection pad layers (main portion of 314 shown in annotated Fig 26), the plurality of package connection terminals (bond pads 304 shown in annotated Fig 26) electrically connecting the lower package (200 Fig 26) with the upper package (300 Fig 26),
wherein the plurality of second redistribution insulating layers (lower portion of 108 shown in annotated Fig 26 and upper portion of 108 shown in annotated Fig 26) include a first insulating layer (outer portion of the lower portion of 108 shown in annotated Fig 26), a second insulating layer (upper portion of 108 shown in annotated Fig 26), and
a third insulating layer (inner portion of the lower portion of 108 shown in annotated Fig 26) stacked on the semiconductor chip (118 Fig 26) and the expanded structure (structure that contains through vias 112 Fig 26),
the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26) include a first wiring layer (layer that includes metallization 106 Fig 26) on the first insulating layer (outer portion of the lower portion of 108 shown in annotated Fig 26) and covered by the second insulating layer (upper portion of 108 shown in annotated Fig 26), and
a second wiring layer (layer that includes 304, 306, and 314 Fig 26) on the second insulating layer (upper portion of 108 shown in annotated Fig 26) and the crack prevention layer (104 Fig 20A), the second wiring layer (314 Fig 26) is partially covered by the third insulating layer (inner portion of the lower portion of 108 shown in annotated Fig 26),
the second wiring layer (layer that includes 304, 306, and 314 Fig 26) includes a plurality of pad portions (lower portion of 314 shown in annotated Fig 26) and a plurality of line portions (306 Fig 26) extending from the plurality of pad portions (lower portion of 314 shown in annotated Fig 26),
the plurality of upper surface connection pad layers (main portion of 314 shown in annotated Fig 26) are on the plurality of pad portions (lower portion of 314 shown in annotated Fig 26), such that the plurality of pad portions (lower portion of 314 shown in annotated Fig 26) and the plurality of upper surface connection pad layers (main portion of 314 shown in annotated Fig 26) form a plurality of upper surface connection pads (304 and 314),
the crack prevention layer (104 Fig 26) overlaps at least some of the plurality of pad portions (portion of 314 shown in annotated Fig 26) in a vertical direction (vertical y direction Fig 26) and covers at least a portion of the second insulating layer (upper portion of 108 shown in annotated Fig 26) such that the crack prevention layer (104 Fig 26) is apart from the first wiring layer (layer that includes metallization 106) in the vertical direction (vertical y direction Fig 26) with a portion of the second insulating layer (upper portion of 108 shown in annotated Fig 26) therebetween.
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Regarding Claim 20, Wang et al discloses the limitations of claim 18 as explained above. Wang et al further discloses
wherein the crack prevention layer comprises an organic material having a modulus lower than a modulus of each of the plurality of second redistribution insulating layers, or the crack prevention layer (dielectric layer 104, which may be silicon oxide or silicon nitride [column 3, lines 18-33]) comprises an inorganic material (silicon nitride or silicon oxide is an inorganic material) having a fracture toughness higher than a fracture toughness of each of the plurality of second redistribution insulating layers (lower and upper portion of dielectric layer 108, which may be polyimide (which is known to be an organic material), [column 3, lines 60-67] shown in annotated Fig 26) (the examiner notes that since the material of the crack prevention layer 104 is the same as the material of the crack prevention layer of the instant application, and the material of the second redistribution insulating layers 108 is the same as in the instant application, the reference Wang et al is considered to meet this limitation) .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 11942435).
Regarding Claim 6, Wang et al discloses
wherein each of the first insulating layer (lower portion of dielectric layer 108, which may be polyimide, [column 3, lines 60-67] shown above in annotated Fig 26) and the second insulating layer (upper portion of dielectric layer 108, which may be polyimide, [column 3, lines 60-67] shown above in annotated Fig 26) is a redistribution insulating layer including an organic material (polyimide is organic).
Wang et al, as applied to claim 1, does not disclose
the crack prevention layer comprises an organic material having a modulus lower than a modulus of the first insulating layer and a modulus of the second insulating layer.
However, in a different embodiment, Wang et al discloses
the crack prevention layer (104 may be a polymer such as BCB or the like [column 3, lines 17-33], which is organic) comprises an organic material having a modulus (BCB has a Young’s modulus of 2.9-3.7 GPa) lower than a modulus (polyimide has a Young’s modulus of 3.0 to 10+ GPa) of the first insulating layer (lower portion of 108 shown above in annotated Fig 26) and a modulus of the second insulating layer (upper portion of 108, shown above in annotated Fig 26).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang et al to include the crack prevention layer made of BCB having a lower modulus than polyimide in order to reduce stress and improve adhesions in packaging applications and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill would have recognized that having the crack prevention layer made of BCB would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 11942435) in view of Kwak et al (US 2013/0020685).
Regarding Claim 11, Wang et al discloses a semiconductor package (package structure 500 [column 15, lines 30-37] Fig 26) comprising:
a first wiring structure (front-side redistribution structure 131 [column 6, lines 15-35] Fig 26) including a plurality of first redistribution patterns (metallization patterns 142, 156 [column 8, lines 45-60], 170 [column 9, lines 45-55] Fig 20A) and a plurality of first redistribution insulating layers (dielectric layers 133, 146 [column 8, lines 40-55], 160, 174 [column 9, lines 60-67] Fig 20A) surrounding the plurality of first redistribution patterns (142, 156, 170 Fig 20A);
a second wiring structure (back-side redistribution structure 110 [column 5, lines 60-67], bond pads 304 [column 13, lines 45-60], through vias 306 [column 13, lines 45-60] and functional connectors 314 [column 14, lines 25-38] Fig 26) on the first wiring structure (131 Fig 26),
the second wiring structure (110, 304, 306, 314 Fig 26) including a plurality of second redistribution patterns (metallization pattern 106 [column 3, lines 60-67] Fig 20A, bonding pads 304, through vias 306, and functional connectors 314 Fig 26), a plurality of second redistribution insulating layers (dielectric layers 104, lower portion of 108, upper portion of 108 [column 3, lines 60-67] Fig 20A, shown in annotated Fig 26) surrounding the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26), a crack prevention layer (dielectric layer 104, which may be silicon oxide or silicon nitride [column 3, lines 18-33]), and a plurality of upper surface connection pad layers (main portion of functional connectors 314 [column 14, lines 25-38] shown in annotated Fig 26);
a semiconductor chip (semiconductor substrate 118 [column 5, lines 13-33] Fig 26) between the first wiring structure (131 Fig 26) and the second wiring structure (110, 304, 306, and 314 Fig 26); and
an expanded structure (structure that contains through vias 112 [column 6, lines 6-15] Fig 26) that electrically connects the plurality of first redistribution patterns (142, 156, 170 Fig 20A) with the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26) and surrounds the semiconductor chip (118 Fig 26),
wherein the plurality of second redistribution insulating layers (lower portion of 108 shown in annotated Fig 26 and upper portion of 108 shown in annotated Fig 26) include a first insulating layer (outer portion of the lower portion of 108 shown in annotated Fig 26), a second insulating layer (upper portion of 108 shown in annotated Fig 26), and
a third insulating layer (inner portion of the lower portion of 108 shown in annotated Fig 26) stacked on the semiconductor chip (118 Fig 26) and the expanded structure (structure that contains through vias 112 Fig 26),
the plurality of second redistribution patterns (106, 304, 306, 314 Fig 26) include a first wiring layer (layer that includes metallization 106 Fig 26) on the first insulating layer (outer portion of the lower portion of 108 shown in annotated Fig 26) and covered by the second insulating layer (upper portion of 108 shown in annotated Fig 26), and
a second wiring layer (layer that includes 304, 306, and 314 Fig 26) on the second insulating layer (upper portion of 108 shown in annotated Fig 26) and the crack prevention layer (104 Fig 20A), the second wiring layer (314 Fig 26) is partially covered by the third insulating layer (inner portion of the lower portion of 108 shown in annotated Fig 26),
the second wiring layer (layer that includes 304, 306, and 314 Fig 26) includes a plurality of pad portions (lower portion of 314 shown in annotated Fig 26) and a plurality of line portions (306 Fig 26) extending from the plurality of pad portions (lower portion of 314 shown in annotated Fig 26),
the plurality of upper surface connection pad layers (main portion of 314 shown in annotated Fig 26) are on the plurality of pad portions (lower portion of 314 shown in annotated Fig 26), such that the plurality of pad portions (lower portion of 314 shown in annotated Fig 26) and the plurality of upper surface connection pad layers (main portion of 314 shown in annotated Fig 26) form a plurality of upper surface connection pads (304 and 314),
the crack prevention layer (104 Fig 26) overlaps at least some of the plurality of pad portions (portion of 314 shown in annotated Fig 26) in a vertical direction (vertical y direction Fig 26) and covers at least a portion of the second insulating layer (upper portion of 108 shown in annotated Fig 26) such that the crack prevention layer (104 Fig 26) is apart from the first wiring layer (layer that includes metallization 106) in the vertical direction (vertical y direction Fig 26) with a portion of the second insulating layer (upper portion of 108 shown in annotated Fig 26) therebetween;
wherein an edge region (region that includes 112 Fig 26) of the semiconductor package (500) surrounds a central region (region that includes 118 Fig 26) of the semiconductor package (500) in a cross-sectional view shown in Fig 26.
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Wang et al does not directly disclose
wherein an edge region of the semiconductor package surrounds a central region of the semiconductor package in a plan view.
Kwak et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein an edge region (region of through vias 141 and 142 [0064] Fig 5) of the semiconductor package (semiconductor package [0004]) surrounds a central region (first region I [0064]) of the semiconductor package in a plan view (shown in Fig 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang et al to include wherein an edge region of the semiconductor package surrounds a central region of the semiconductor package in a plan view as taught by Kwak et al in order to provide electrical connection around the semiconductor chip and improve structural support for the package. Further, a person of ordinary skill in the art would have recognized that having via type structures that surround the semiconductor chip in a plan view would be advantageous in structural support and would improve the reliability and durability of the device (see MPEP 2143.I(D)).
Regarding Claim 12, the combination of Wang et al and Kwak et al discloses the limitations of claim 11 as explained above. The combination of Wang et al and Kwak et al further discloses
wherein the crack prevention layer (104 Fig 26 Wang et al) completely covers an upper surface of the second insulating layer (upper portion of 108 shown above in annotated Fig 26 Wang et al).
Regarding Claim 13, the combination of Wang et al and Kwak et al discloses the limitations of claim 11 as explained above. The combination of Wang et al and Kwak et al further discloses
wherein the crack prevention layer (104 Fig 26 Wang et al) covers lower surfaces of at least some of the plurality of pad portions (lower portion of 314 shown above in annotated Fig 26 Wang et al), and
the crack prevention layer (104 Fig 26 Wang et al) comprises a plurality of crack prevention layers (104 Wang et al that covers the through vias 141 and 142 shown in Fig 5 Kwak et al) having edges extending from edges of the at least some of the plurality of pad portions (lower portion of 314 shown above in annotated Fig 26 Wang et al would be attached to through vias 141 and 142 Fig 5 Kwak et al, and would be considered to meet the limitation in the combination applied) to the outside by a first distance in a horizontal direction (horizontal x direction Fig 5 Kwak et al) in a plan view (edge region is the region of through vias 141 and 142 Fig 5 Kwak et al).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 11942435) in view of Meyer et al (US 2013/0328191) and in further view of Scharf et al (US 2015/0162319).
Regarding Claim 19, Wang et al discloses the limitations of claim 18 as explained above. Wang et al does not directly disclose
wherein a thickness of the first wiring layer is 4 µm to 8 µm,
a thickness of the crack prevention layer is equal to or greater than the thickness of the first wiring layer, and
the thickness of the crack prevention layer is 4 µm to 10 µm.
Meyer et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
the thickness of the dielectric layer is 5 µm to 15 µm [0003].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang et al to include wherein the thickness of the crack prevention layer is 4 µm to 10 µm as taught by Meyer et al in order to increase the value of Young’s modulus [0002] which would improve the structural stability and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the thickness of the crack prevention layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Wang et al and Meyer et al does not directly disclose
wherein a thickness of the first wiring layer is 4 µm to 8 µm, and
a thickness of the crack prevention layer is equal to or greater than the thickness of the first wiring layer.
Scharf et al, in the related art of semiconductor devices that include semiconductor packaging devices, discloses
wherein a thickness of the first wiring layer (first wiring layer 9 [0034] Fig 3) is 5 µm to 50 µm.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Wang et al and Meyer et al to include wherein a thickness of the first wiring layer is 4 µm to 8 µm as taught by Scharf et al in order to optimize the electrical conductive function of the device while providing structural support and minimizing the risk of unwanted damage, and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the thickness of the first wiring layer since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Wang et al, Meyer et al, and Scharf et al now discloses
a thickness of the crack prevention layer (104, Fig 26 Wang et al) is equal to or greater than the thickness of the first wiring layer (106 Fig 26 Wang et al/9 Fig 3 Scharf et al).
Allowable Subject Matter
Claims 3, 8, 9, 14, 15, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3: The prior art does not anticipate or render obvious, alone or in combination, that “wherein the crack prevention layer only covers a portion overlapping the pad portion in the vertical direction and a portion adjacent to the edge of the pad portion in a plan view, of a surface of the second insulating layer facing the second wiring layer,” in the combination required by the claim.
Claim 8: The prior art does not anticipate or render obvious, alone or in combination, that “wherein a side surface of the third insulating layer and a side surface of the connection pad layer are apart from each other to define a delamination space therebetween,” in the combination required by the claim.
Specifically, the reference Wang et al does not disclose a delamination space where a side surface of the third insulating layer and a side surface of the connection pad layer are apart from each other. Further, should another reference be found that would disclose this feature, it would not be obvious to a person of ordinary skill in the art to make the alteration to Wang et al.
Claim 9 would be allowable based on its dependency on Claim 8.
Claim 14: The prior art does not anticipate or render obvious, alone or in combination, that “wherein the plurality of upper surface connection pads include first upper surface connection pads in the central region and second upper surface connection pads in the edge region,” in the combination required by the claim.
Specifically, regarding Claim 14, this is because although the reference Wang et al teaches that the plurality of upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) include second upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the edge region (region of 141 and 142 shown in Fig 5 Kwak et al), Wang et al does not teach first upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the central region (region of the semiconductor die, Wang et al). Further, should a secondary reference be found that teaches the first upper surface connection pads in the central region, it would not be directly obvious to a person of ordinary skill in the art to alter the combination of Wang et al and Kwak et al in this manner.
Claim 15: The prior art does not anticipate or render obvious, alone or in combination, that “wherein the plurality of upper surface connection pads include first upper surface connection pads in the central region and second upper surface connection pads in the edge region,” in the combination required by the claim.
Specifically, regarding Claim 15, this is because although the reference Wang et al teaches that the plurality of upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) include second upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the edge region (region of 141 and 142 shown in Fig 5 Kwak et al), Wang et al does not teach first upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the central region (region of the semiconductor die, Wang et al). Further, should a secondary reference be found that teaches the first upper surface connection pads in the central region, it would not be directly obvious to a person of ordinary skill in the art to alter the combination of Wang et al and Kwak et al in this manner.
Claim 16: The prior art does not anticipate or render obvious, alone or in combination, that “wherein the plurality of upper surface connection pads include first upper surface connection pads in the central region and second upper surface connection pads in the edge region,” in the combination required by the claim.
Specifically, regarding Claim 16, this is because although the reference Wang et al teaches that the plurality of upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) include second upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the edge region (region of 141 and 142 shown in Fig 5 Kwak et al), Wang et al does not teach first upper surface connection pads (main portion of 314 shown above in annotated Fig 26 Wang et al) in the central region (region of the semiconductor die, Wang et al). Further, should a secondary reference be found that teaches the first upper surface connection pads in the central region, it would not be directly obvious to a person of ordinary skill in the art to alter the combination of Wang et al and Kwak et al in this manner.
Claim 17: The prior art does not anticipate or render obvious, alone or in combination, that “wherein a vertical level of an upper surface of each of the plurality of upper surface connection pad layers is lower than a vertical level of an upper surface of the third insulating layer, such that the plurality of upper surface connection pad layers are recessed into the third insulating layer, and side surfaces of at least some of the plurality of upper surface connection pad layers and a side surface of the third insulating layer are spaced apart from each other to define a delamination space therebetween,” in the combination required by the claim.
Specifically, regarding Claim 17, this is because the upper surface of the plurality of upper surface connection pad layers (main portion of 314 shown above in annotated Fig 26 Wang et al) is above any vertical level of the third insulating layer (inner portion of the lower portion of 108 shown in annotated Fig 26) and does not meet the limitation of the claim. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to make the alteration to the combination of Wang et al and Kwak et al as applied above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al (US 2020/0051928) which discloses a semiconductor package with a conductive crack preventing layer [0060], and Funaya et al (US 2015/0206934) which discloses a semiconductor package with embedded semiconductor chips [0114].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812