Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al. (USPGPUB 2021/0350217).
Regarding claims 1 and 16, Tran et al. disclose a computing system and method (figs. 1 – 39) comprising: a network controller (figs. 1, 9); and a processor coupled to the network controller, wherein the processor includes logic coupled to one or more substrates (paragraph 0009, 0017; fig. 5), the logic including: a capacitor ladder (3901, fig. 39) , a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply and accumulate (MAC) operations during a computation phase (paragraph 0006, figs. 22 – 27, 39), and a successive approximation register (SAR) (see fig. 39) coupled to the capacitor ladder (3901, fig. 39) , the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase (paragraphs 0182 – 0184).
Regarding claim 8, Tran et al. semiconductor apparatus (figs. 1 – 3), comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (paragraph 0009, 0017; fig. 5), the logic including: a capacitor ladder (3901, fig. 39); a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply and accumulate (MAC) operations during a computation phase (paragraph 0006, figs. 22 – 27, 39) and a successive approximation register (SAR) (SAR) (see fig. 39) coupled to the capacitor ladder (3901, fig. 39) the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase (paragraphs 0182 – 0184).
Regarding claims 2 and 17, Tran et al. disclose a computing system and method (figs. 1 – 39), wherein the logic further includes a comparator (see figs. 39 for the comparator) coupled to the capacitor ladder (3901, fig. 39) and the SAR (see fig. 39), wherein the results of the multi-bit MAC operations are to be digitized via the comparator (paragraphs 0182 – 0184).
Regarding claims 3 and 18, Tran et al. disclose a computing system and method (figs. 1 – 39) wherein the logic is to apply a rectified linear unit activation function to the digitized results (paragraphs 0182 – 0184).
Regarding claims 4 and 19, Tran et al. disclose a computing system and method (figs. 1 – 39), wherein the SAR is to determine a polarity of the results based on most significant bits in the results (paragraphs 0182 – 0184).
Regarding claims 5 and 20, Tran et al. disclose a computing system and method (figs. 1 – 39), wherein the SAR is to bypass digitization of least significant bits in the results if the polarity is negative (paragraphs 0182 – 0184; fig. 27C)..
Regarding claim 6, Tran et al. disclose a computing system (figs. 1 – 39), wherein the SAR is to complete digitization of least significant bits in the results if the polarity is positive (paragraphs 0182 – 0184; fig. 27C).
Regarding claim 7, Tran et al. disclose a computing system (figs. 1 – 39),, wherein the capacitor ladder includes a C-2C ladder (fig. 37, 39).
Regarding claim 9, Tran et al. semiconductor apparatus (figs. 1 – 3), further including a comparator coupled to the capacitor ladder and the SAR, wherein the results of the multi-bit MAC operations are to be digitized via the comparator (paragraphs 0182 – 0184; fig. 27C).
Regarding claim 10, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the logic is to apply a rectified linear unit activation function to the digitized results (paragraphs 0182 – 0184; fig. 27C).
Regarding claim 11, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the SAR is to determine a polarity of the results based on most significant bits in the results (paragraphs 0182 – 0184; fig. 27C).
. Regarding claim 12, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the SAR is to bypass digitization of least significant bits in the results if the polarity is negative (paragraphs 0182 – 0184; fig. 27C).
. Regarding claim 13, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the SAR is to complete digitization of least significant bits in the results if the polarity is positive (paragraphs 0182 – 0184; fig. 27C). .
Regarding claim 14, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the capacitor ladder includes a C-2C ladder (fig. 36).
Regarding claim 15, Tran et al. semiconductor apparatus (figs. 1 – 3),, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates (paragraphs 0182 – 0184; fig. 27C).
. Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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