DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Applicant’s Amendment and Remarks filed on 11/26/2025. Claims 1-20 have been amended. Claims 1-20 are present for examination.
The 35 USC 101 rejections of claims 1-20 have been withdrawn in view of the amendments and remarks.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 in view of Goel have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 2 is objected to because of the following informalities: “shading operations”should be “shader operations”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 7-9, 12, 14-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Publication No. 20140098117 to Goel et al. in view of Japanese Patent Publication No. JP 2006243937 A to Yamada.
Regarding claim 1, Goel discloses a method comprising: in response to identifying, at a processing unit, a quad primitive of a scene to be rendered by the processing unit, loading a set of four vertices representing the quad primitive for a pixel shader (Goel, para. [0025], disclosing rendering corresponding to converting 3D graphics primitives that correspond to 3D objects in a graphics scene into 2D rasterized image data, para. [0026], disclosing to render 3D graphics primitives of a particular type, a user application executing on a host CPU may set up the state of the GPU to render primitives of that particular type, and place geometry data corresponding to the primitive to be rendered onto a GPU-accessible memory, setting up the state of the GPU may involve issuing state commands to the GPU that indicate a particular type of primitive that is to be rendered by the GPU and binding one or more types of shader programs to the GPU pipeline, placing the geometry data into the GPU-accessible memory may involve populating one or more vertex buffers in the GPU-accessible memory with vertices and/or control points that correspond to the primitives to be rendered, para. [0034], disclosing determining a primitive type associated with one or more vertices to be processed, and configure one or more stages to of the 3D graphics pipeline to process the vertices based on the primitive type, the data indicative of the primitive type may be provided to one or more processing stages in the graphics rendering pipeline so that such stages can process the received data based on the primitive type corresponding to the received data, para. [0081], disclosing a primitive to be rendered can be determined to be a three control point patch primitive or a four control point patch primitive, para. [0093], disclosing processing units to render the geometry represented by vertices in memory based on primitive type data, para. [0094], disclosing the programmable shader units in processing units may include pixel shader units, para. [0099], disclosing resources block may store vertex buffers, para. [0101], disclosing pixel shader (PS) may retrieve/receive data from resources block, para. [0203], disclosing reading data included in an index slot of the index buffer and retrieving corresponding vertices from the vertex buffer, indicating when a primitive to be rendered is of a particular type (such as four control point patch primitive as quad), the host CPU can identity the type of the first primitive (four control point patch primitive or quad), and in response to identifying the primitive of that particular type (four control point patch primitive or quad), the GPU state is set up to indicate the particular type (four control point patch primitive or quad) of primitive is to be rendered, and shader programs are bound to the GPU pipeline accordingly, the vertices data of the primitive (four control point patch primitive or quad indicating four vertices data) is placed (loaded) into the GPU-accessible memory for a pixel shader. See also, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the IA can in response to the primitive type (triangle or quad) to load different number of vertices for further processing); and executing, by the pixel shader, one or more shader operations for the quad primitive using the set of four vertices (Goel, para. [0093], disclosing processing units to render the geometry represented by vertices in memory based on primitive type data, para. [0094], disclosing the programmable shader units in processing units may include pixel shader units, para. [0099], disclosing resources block may store vertex buffers, para. [0100], disclosing the pixel shader as a programmable stage to execute a shader program of a particular type, para. [0101], disclosing pixel shader (PS) may retrieve/receive data from resources block, para. [0203], disclosing reading data included in an index slot of the index buffer and retrieving corresponding vertices from the vertex buffer, FIG. 8, showing the data such as a quad is processed with the rendering pipeline including the pixel shader (PS) with triangle stream including the set of four vertices presenting the quad primitive (patches 4), para. [0179], disclosing a graphics pipeline using a draw call instruction to render primitives, indicating the quad primitive is processed using the loaded set of four vertices with the processing units including the pixel shader, indicating the pixel shader can execute shader programs as one or more shader operations for the quad primitive using the triangle stream output for the rasterizer including the set of four vertices representing the quad primitive).
However, Goel does not expressly disclose in response to rasterizing, at a processing unit, a quad primitive of a scene to be rendered by the processing unit, loading a set of four vertices representing the quad primitive for a pixel shader.
On the other hand, Yamada discloses in response to rasterizing, at a processing unit, a quad primitive of a scene to be rendered by the processing unit, loading a set of four vertices representing the quad primitive for a pixel shader (Yamada, Translation, para. [0019], disclosing the rendering processing device divides the shape of an object to be rendered and converts it into a set of geometric primitives, para. [0020], disclosing the rasterizer acquires vertex data of the primitive to be drawn, a drawing primitive can be rectangle, para. [0028], disclosing the rasterizer receives as input a square primitive, para. [0052], disclosing the pixel shader applies parametric surface patches to the square primitives distributed from the rasterizer, and performs processing to subdivide the shape of the object to be drawn into a mesh in units of patches, the pixel shader divides the patch into meshes by determining the points on the parametric surface corresponding to the two-dimensional parameter coordinate values (u,v) generated by the rasterizer as the vertex coordinates of the meshes, the pixel shader requires data on the control points that determine the shape of the patch, Yamada, FIG. 3, showing the control points representing the patch corresponding to the square primitives of the rasterizer, indicating the control points including a set of four vertices representing the square primitive can be loaded for a pixel shader in response to rasterizing the square primitive).
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Before the invention was effectively filed, it would have been obvious for a person skilled in the art to combine Goel and Yamada. The suggestion/motivation would have been to generate a curved surface of any rectangular area based on square primitive inputs to the rasterizer, as suggested by Yamada (see Yamada, Translation, para. [0036]).
Regarding claim 2, Goel in view of Yamada discloses the method of claim 1, wherein loading the set of four vertices comprises: loading attributes of the set of four vertices to a local data store used by the pixel shader to execute the one or more shading operations for the quad primitive (Goel, para. [0026], disclosing to render 3D graphics primitives of a particular type, a user application executing on a host CPU may set up the state of the GPU to render primitives of that particular type, and place geometry data corresponding to the primitive to be rendered onto a GPU-accessible memory, setting up the state of the GPU may involve issuing state commands to the GPU that indicate a particular type of primitive that is to be rendered by the GPU and binding one or more types of shader programs to the GPU pipeline, placing the geometry data into the GPU-accessible memory may involve populating one or more vertex buffers in the GPU-accessible memory with vertices and/or control points that correspond to the primitives to be rendered, para. [0034], disclosing determining a primitive type associated with one or more vertices to be processed, and configure one or more stages to of the 3D graphics pipeline to process the vertices based on the primitive type, the data indicative of the primitive type may be provided to one or more processing stages in the graphics rendering pipeline so that such stages can process the received data based on the primitive type corresponding to the received data, para. [0093], disclosing processing units to render the geometry represented by vertices in memory based on primitive type data, para. [0094], disclosing the programmable shader units in processing units may include pixel shader units, para. [0099], disclosing resources block may store vertex buffers, para. [0100], disclosing the pixel shader as a programmable stage to execute a shader program of a particular type, para. [0101], disclosing pixel shader (PS) may retrieve/receive data from resources block, para. [0103], disclosing each of vertices may include one or more attributes, para. [0203], disclosing reading data included in an index slot of the index buffer and retrieving corresponding vertices from the vertex buffer, FIG. 8, showing the data such as a quad is processed with the rendering pipeline including the pixel shader (PS), para. [0179], disclosing a graphics pipeline using a draw call instruction to render primitives, indicating the vertex buffer in the resources block can correspond to a local data store used by the pixel shader and the attributes of the set of four vertices of the quad primitive of a quad is loaded in the vertex buffer to execute the one or more shader programs as the shading operations for the quad primitive).
Regarding claim 5, Goel in view of Yamada discloses the method of claim 1, further comprising: in response to rasterizing a non-quad primitive, loading a set of three vertices representing the non-quad primitive for the pixel shader (Goel, para. [0026], disclosing to render 3D graphics primitives of a particular type, a user application executing on a host CPU may set up the state of the GPU to render primitives of that particular type, and place geometry data corresponding to the primitive to be rendered onto a GPU-accessible memory, setting up the state of the GPU may involve issuing state commands to the GPU that indicate a particular type of primitive that is to be rendered by the GPU and binding one or more types of shader programs to the GPU pipeline, placing the geometry data into the GPU-accessible memory may involve populating one or more vertex buffers in the GPU-accessible memory with vertices and/or control points that correspond to the primitives to be rendered, para. [0034], disclosing determining a primitive type associated with one or more vertices to be processed, and configure one or more stages to of the 3D graphics pipeline to process the vertices based on the primitive type, the data indicative of the primitive type may be provided to one or more processing stages in the graphics rendering pipeline so that such stages can process the received data based on the primitive type corresponding to the received data, para. [0081], disclosing a primitive to be rendered can be determined to be a three control point patch primitive or a four control point patch primitive, para. [0093], disclosing processing units to render the geometry represented by vertices in memory based on primitive type data, para. [0094], disclosing the programmable shader units in processing units may include pixel shader units, para. [0099], disclosing resources block may store vertex buffers, para. [0101], disclosing pixel shader (PS) may retrieve/receive data from resources block, FIG. 8, showing when triangles as primitive type, triangle stream is passed through rasterizer to Pixel Shader, para. [0146], disclosing the rasterization to rasterize triangles in a triangle stream, para. [0203], disclosing reading data included in an index slot of the index buffer and retrieving corresponding vertices from the vertex buffer, indicating when a primitive to be rendered is of a particular type, such as three control point patch primitive as non-quad or triangle, the host CPU can identity the type of the non-quad primitive (three control point patch primitive or non-quad or triangle), and in response to identifying the primitive of that particular type (three control point patch primitive or non-quad or triangle), the GPU state is set up to indicate the particular type (three control point patch primitive or non-quad or triangle) of primitive is to be rendered, rasterizing the non-quad (triangle) primitives, and shader programs are bound to the GPU pipeline accordingly, the vertices data of the primitive (three control point patch primitive or non-quad or triangle indicating three vertices data) is placed (loaded) into the GPU-accessible memory for a pixel shader in response to rasterizing non-quad (triangle) primitives. See also, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the IA can in response to the primitive type (triangle or quad) to load different number of vertices for further processing); and executing a shader operation for the non-quad primitive using the loaded three vertices (Goel, para. [0093], disclosing processing units to render the geometry represented by vertices in memory based on primitive type data, para. [0094], disclosing the programmable shader units in processing units may include pixel shader units, para. [0099], disclosing resources block may store vertex buffers, para. [0100], disclosing the pixel shader as a programmable stage to execute a shader program of a particular type, para. [0101], disclosing pixel shader (PS) may retrieve/receive data from resources block, para. [0203], disclosing reading data included in an index slot of the index buffer and retrieving corresponding vertices from the vertex buffer, FIG. 8, showing the data such as a triangle is processed with the rendering pipeline including the pixel shader (PS), para. [0179], disclosing a graphics pipeline using a draw call instruction to render primitives, indicating the non-quad primitive or triangle is processed by executing a shader program as a shader operation for the non-quad primitive using the set of three vertices with the processing units including the pixel shader).
Regarding claim 7, Goel in view of Yamada discloses the method of claim 1, further comprising: identifying a first primitive as the quad primitive in response to a software instruction (Goel, para. [0033], disclosing rendering a plurality of different primitive types during the execution of a draw call command, the first primitive type may be a three control point patch and the second primitive type may be a four control point patch, para. [0034], disclosing determining a primitive type associated with one or more vertices to be processed during the execution of a draw call command, and configure one or more stages to of the 3D graphics pipeline to process the vertices based on the primitive type, the data indicative of the primitive type may be provided to one or more processing stages in the graphics rendering pipeline so that such stages can process the received data based on the primitive type corresponding to the received data, para. [0081], disclosing a primitive to be rendered can be determined to be a three control point patch primitive or a four control point patch primitive, indicating the draw call command can correspond to a software instruction, and determining a primitive type can correspond to identifying a first primitive as the quad primitive (a four control point patch primitive) in response to the draw call command as a software instruction).
Regarding claim 8, it recites similar limitations of claim 1 but in a processing unit form. The rationale of claim 1 rejection is applied to reject claim 8. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 9, it recites similar limitations of claim 2 but in a processing unit form. The rationale of claim 2 rejection is applied to reject claim 9. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 12, it recites similar limitations of claim 5 but in a processing unit form. The rationale of claim 5 rejection is applied to reject claim 12. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 14, it recites similar limitations of claim 7 but in a processing unit form. The rationale of claim 7 rejection is applied to reject claim 14. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 15, it recites similar limitations of claim 1 but in a processing system form. The rationale of claim 1 rejection is applied to reject claim 15. In addition, Goel discloses a first processing unit, and a second processing unit having scheduler circuitry and shader circuitry (Goel, FIG. 1, showing a computing device including a CPU, a GPU, and a BUS, FIG. 2, showing CPU includes software application, graphics API, GPU driver, operating system, GPU includes command engine and processing units, para. [0092], disclosing GPU driver receives instructions from software application and controls the operation of GPU, para. [0093], disclosing command engine to retrieve and execute commands, cause processing units to render geometry represented by vertices in memory based on primitive type data stored in memory, para. [0098], disclosing graphics pipeline including resources block and processing stages including input assembler and pixel shader, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the GPU and/or the processing units can correspond to the scheduler circuitry and the shader circuitry).
Regarding claim 16, it recites similar limitations of claim 2 but in a processing system form. The rationale of claim 2 rejection is applied to reject claim 16. In addition, Goel discloses a first processing unit, and a second processing unit having scheduler circuitry and shader circuitry (Goel, FIG. 1, showing a computing device including a CPU, a GPU, and a BUS, FIG. 2, showing CPU includes software application, graphics API, GPU driver, operating system, GPU includes command engine and processing units, para. [0092], disclosing GPU driver receives instructions from software application and controls the operation of GPU, para. [0093], disclosing command engine to retrieve and execute commands, cause processing units to render geometry represented by vertices in memory based on primitive type data stored in memory, para. [0098], disclosing graphics pipeline including resources block and processing stages including input assembler and pixel shader, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the GPU and/or the processing units can correspond to the scheduler circuitry and the shader circuitry).
Regarding claim 19, it recites similar limitations of claim 5 but in a processing system form. The rationale of claim 5 rejection is applied to reject claim 19. In addition, Goel discloses a first processing unit, and a second processing unit having scheduler circuitry and shader circuitry (Goel, FIG. 1, showing a computing device including a CPU, a GPU, and a BUS, FIG. 2, showing CPU includes software application, graphics API, GPU driver, operating system, GPU includes command engine and processing units, para. [0092], disclosing GPU driver receives instructions from software application and controls the operation of GPU, para. [0093], disclosing command engine to retrieve and execute commands, cause processing units to render geometry represented by vertices in memory based on primitive type data stored in memory, para. [0098], disclosing graphics pipeline including resources block and processing stages including input assembler and pixel shader, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the GPU and/or the processing units can correspond to the scheduler circuitry and the shader circuitry).
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel in view of Yamada, and further in view of Bloomenthal (Bloomenthal, Barycentric Quad Rasterization).
Regarding claim 4, Goel in view of Yamada discloses the method of claim 1. However, Goel or Yamada does not expressly disclose wherein the one or more shader operations comprises interpolating the quad primitive using the set of four vertices.
On the other hand, Bloomenthal discloses the one or more shader operations comprises interpolating the quad primitive using the set of four vertices (Bloomenthal, p. 68, Sec. 3, 1st para., disclosing for each pixel within the quad, computing generalized barycentric coordinates of the pixel with respect to the screen positions of the four quad corners, and the coordinates serve as weighting coefficients to interpolate vertex attributes, Figure 8, showing compute p within the quad using weighted interpolation, indicating the one or more shader operations for the quad primitive by interpolating the quad using the set of four vertices representing the quad).
Before the invention was effectively filed, it would have been obvious for a person skilled in the art to combine Goel in view of Yamada with Bloomenthal. The suggestion/motivation would have been to eliminate quad split C1 discontinuity, as suggested by Bloomenthal (see Bloomenthal, p. 68, Sec. 3, 1st para.).
Regarding claim 11, it recites similar limitations of claim 4 but in a processing unit form. The rationale of claim 4 rejection is applied to reject claim 11. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 18, it recites similar limitations of claim 4 but in a processing system form. The rationale of claim 4 rejection is applied to reject claim 18. In addition, Goel discloses a first processing unit, and a second processing unit having scheduler circuitry and shader circuitry (Goel, FIG. 1, showing a computing device including a CPU, a GPU, and a BUS, FIG. 2, showing CPU includes software application, graphics API, GPU driver, operating system, GPU includes command engine and processing units, para. [0092], disclosing GPU driver receives instructions from software application and controls the operation of GPU, para. [0093], disclosing command engine to retrieve and execute commands, cause processing units to render geometry represented by vertices in memory based on primitive type data stored in memory, para. [0098], disclosing graphics pipeline including resources block and processing stages including input assembler and pixel shader, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the GPU and/or the processing units can correspond to the scheduler circuitry and the shader circuitry).
Claim(s) 6, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goel in view of Yamada, and further in view of US Patent No. 7440879 B2 to Breitfeld et al.
Regarding claim 6, Goel in view of Yamada discloses the method of claim 1. However, Goel or Yamada does not expressly disclose further comprising: identifying a first primitive as the quad primitive based on an indicator generated by a compiler of code that generates the first primitive.
On the other hand, Breitfeld discloses identifying a first primitive as the quad primitive based on an indicator generated by a compiler of code that generates the first primitive (Breitfeld, Fig. 1, showing meshing a CAD model to obtain finite element mesh and extract information such as positions of grid points, corners, edges, types of finite elements, col. 9, lines 7-12, disclosing meshing tool using an information-forwarding interface to mesh the model to generate finite element mesh, col. 11, lines 25-38, disclosing extracting information from the finite element mesh via an additional information-forwarding interface, and the extracted information including if it is a two-dimensional element, whether it is a triangle, a quadrangle, or another type of two-dimensional element, indicating the finite element mesh is generated by a meshing tool with information-forwarding interface corresponding to a compiler of code, the mesh include the first primitive, and information about the mesh including the first primitive is extracted, the extracted information including indicator that identifying the type of the two-dimensional element (corresponding to the first primitive) in the finite element mesh, such as a triangle, a quadrangle, or another type of two-dimensional element, the quadrangle is a quad primitive can be identified based on the extracted element type information corresponding to the indicator).
Before the invention was effectively filed, it would have been obvious for a person skilled in the art to combine Goel in view of Yamada with Breitfeld. The suggestion/motivation would have been to classify finite elements, as suggested by Breitfeld (see Breitfeld, col. 13, lines 59-67).
Regarding claim 13, it recites similar limitations of claim 6 but in a processing unit form. The rationale of claim 6 rejection is applied to reject claim 13. In addition, Goel discloses scheduler circuitry and shader circuitry (Goel, para. [0086], disclosing CPU, GPU and memory of computing device, para. [0087], disclosing the CPU can execute software application, graphics API, GPU driver, and operating system, GPU includes command engine and processing units that may form a 3D graphics rendering pipeline, indicating the computing device (or the CPU and GPU) can correspond to a processing unit, CPU can correspond to the scheduler circuitry and the GPU can correspond to the shader circuitry).
Regarding claim 20, it recites similar limitations of claim 6 but in a processing system form. The rationale of claim 6 rejection is applied to reject claim 20. In addition, Goel discloses a first processing unit, and a second processing unit having scheduler circuitry and shader circuitry (Goel, FIG. 1, showing a computing device including a CPU, a GPU, and a BUS, FIG. 2, showing CPU includes software application, graphics API, GPU driver, operating system, GPU includes command engine and processing units, para. [0092], disclosing GPU driver receives instructions from software application and controls the operation of GPU, para. [0093], disclosing command engine to retrieve and execute commands, cause processing units to render geometry represented by vertices in memory based on primitive type data stored in memory, para. [0098], disclosing graphics pipeline including resources block and processing stages including input assembler and pixel shader, para. [0111], disclosing the input assembler may determine the primitive type, para. [0201], disclosing the IA stage may load different number of vertices based on primitive types, indicating the GPU and/or the processing units can correspond to the scheduler circuitry and the shader circuitry).
Allowable Subject Matter
Claims 3, 10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, none of the prior art references on the record discloses in response to identifying a first primitive as the quad primitive, reconfiguring loading circuitry of the processing unit from loading sets of three vertices representing the quad primitive to loading the set of four vertices representing the quad primitive to a memory associated with the pixel shader.
Claims 10 and 17 respectively recite similar limitations discussed above with respect to claim 3.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HAIXIA DU/Primary Examiner, Art Unit 2611