DETAILED ACTION
This Office action is in response to the communication filed on December 16, 2025. Claims 1-19 remain pending and claim 20 has been added in this application. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application filed March 19, 2020 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged and considered.
Response to Arguments
Applicant’s arguments with respect to amended claims 1, 6, and 10 in the Remarks section (pages 6-11) have been fully considered but are moot because the arguments do not apply to the current combination of references being used in the current rejection.
U.S. Patent Publication 2006/0232505 A1 by Asada in view of U.S. Patent Publication 2017/0004769 A1 by Arokia et al. (“Arokia,”) and further in view of U.S. Patent Publication 2020/0243006 A1 by Kim et al. (“Kim”) and U.S. Patent Publication 2021/0028259 A1 by Xu et al. (“Xu”) address the limitations set forth in the amended claim 1 as the new grounds for rejection.
Applicant argues the first extension portion and the second extension portion are both extended along a first direction, the main body portion is extended along a second direction, and the first direction intersects the second direction, the powerline connection is between two sub-pixels in the first direction and is shared by the two sub-pixels.
Previously, it was not required that the first direction and the second direction are both parallel to a plate surface of the base substrate. Therefore, Asada, Arokia and Kim teaches two sub-pixels along the first (column) direction of the contact hole did share the same VDD line, therefore, meeting claim limitations. However, with the new restriction on the first direction, further art is now cited that also addresses this. Please see below.
Applicant's arguments have been fully considered with respect to 2-5, 7-9, and 11-20 in the Remarks section (pages 10-11) but they are not persuasive as the claims depend upon the features recited in the amended independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-9, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2006/0232505 A1 by Asada in view of U.S. Patent Publication 2017/0004769 A1 by Arokia, and further in view of U.S. Patent Publication 2020/0243006 A1 by Kim and U.S. Patent Publication 2021/0028259 A1 by Xu.
Regarding claim 1, Asada teaches the display with a pixel circuit (Fig. 2 was a pixel driving circuit of a display), and the pixel circuit comprises a data writing sub-circuit (Fig. 3, transistor 103), a storage sub-circuit (Fig. 3, storage capacitor CH) and a driving sub-circuit (Fig. 3, transistor 302),
the data writing sub-circuit is electrically connected with a first terminal of the storage sub-circuit (Fig. 3, terminal of transistor Qn connected to a first terminal of capacitor CH), and is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal (Fig. 3, data signal Vd transmitted according to scanning signal 101 to the first terminal of the capacitor CH);
the driving sub-circuit comprises a control electrode (Fig. 3, gate electrode of transistor 302), a first electrode (Fig. 3, terminal of transistor 302 connected to scanning line 101) and a second electrode (Fig. 3, terminal of transistor 302 connected to first terminal of resistor RL), and the control electrode is electrically connected with the first terminal of the storage sub-circuit (Fig. 3, gate electrode of transistor 302 connected to the first terminal of capacitor CH).
However, Asada does not teach display substrate, comprising a base substrate and a sub-pixel on the base substrate, the first electrode of the driving sub-circuit is configured to receive a first power supply voltage, a second terminal of the resistance device is configured to be electrically connected with a first electrode of a light-emitting element, and the driving sub-circuit is configured to drive the light-emitting element to emit light.
Asada provides a resistor provides stability when a voltage shift referred to as feed-through voltage occurs through the capacitance between the gate and source of the transistor (Qn) when the data signal transferred to the pixel electrode 5903 is held by the storage capacitor 5906. In the analogous art of active matrix pixel circuits, Arokia similarly teaches a feedback circuit between a storage capacitor and OLED light emitting display element on a display substrate (Arokia Fig. 1; [0012]). The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels (Arokia [0011]). The feedback circuit comprising a resistor connected between the second terminal of said drive use transistor and a supply potential and provided a voltage is used to adjust the programming voltage of the pixel (Arokia [0010]). It would have been obvious before the effective filing date of the invention to have switched the liquid crystal with the light emitting element and driving transistor providing a current. As current through OLED strongly depends on the characteristic parameters of the driving and programming TFT. Since the characteristic parameters of a TFT, particularly, the threshold voltage under bias stress, vary by time, and such changes may differ from pixel to pixel, the induced image distortion may be unacceptably high. The programming voltage can be accurately adjusted by an external control unit through the use of feedback voltage generated by the on-pixel feedback circuit. The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current by the driving transistor despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels. One of the methods that has been employed to make the current driving circuit less sensitive to the shift in the threshold voltage is programming the pixel with current instead of voltage (Arokia Fig. 1; [0010]-[0011] and [0007]).
Asada in view of Arokia does not teach:
the base substrate comprises a contact hole region configured to provide a power voltage to the pixel circuit, and the display substrate further comprises a powerline connection electrode electrically connected to the contact hole region;
the powerline connection electrode comprises a main body portion, and a first extension portion and a second first extension portion extended from the main body portion; and first extension portion and the second extension portion are both extended along a first direction, the main body portion is extended along a second direction, and the first direction intersects the second direction.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a second gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The width of the gate electrode was a first direction the connection extended and it was further extended in a first direction by the opposite end of the gate electrode with respect to the contact hole, wherein the this direction of the original ELVDD was in a plane higher intersecting the upper gate electrode 134a of the dual gate electrode structure (Kim Fig. 8; [0097]-[0098]). It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Asada in view of Arokia and Kim does not teach the first direction and the second direction are both parallel to a plate surface of the base substrate.
In the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD). Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other, parallel to a base substrate plane such as the base substrate of Asada as modified (Xu Fig. 3; [0033]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Regarding claim 2, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein the first extension portion and the second extension portion are respectively extended from two ends of the main body portion along the first direction and in opposite directions.
In the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD). Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other, parallel to a base substrate plane such as the base substrate of Asada as modified (Xu Fig. 3; [0033]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Regarding claim 3, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein a length direction of the sub-pixel is parallel to the second direction, and the main body portion is longer than both the first extension portion and the second extension portion.
In the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD). Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other, parallel to a base substrate plane such as the base substrate of Asada as modified (Xu Fig. 3; [0033]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Regarding claim 4, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein a pattern of the powerline connection electrode is an axial symmetry pattern with an axis parallel to the second direction.
In the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD), providing mirror symmetry along column axis. Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other, parallel to a base substrate plane such as the base substrate of Asada as modified (Xu Fig. 3; [0032]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Regarding claim 5, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein the contact hole region is between two sub-pixels adjacent in the first direction (Applicant in Specification paragraph [00214]-[00219] describes cross-shaped connection electrode 325 as connected to the contact hole region in the base substrate and alternately distributed in a first direction D1 and was located at a boundary of sub-pixel rows. A connection electrode 324 or 325 was provided between every two data line connection portions arranged at intervals in the first direction. While two sub-pixels adjacent in the second direction could share one data line connection portion, however these were data connection portions and also in the second direction but not the first direction where connection electrode 325 was oriented. Therefore, for the purposes of examination, the connection electrode located at a boundary of two pixels is shared by two sub-pixels.)
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The width of the gate electrode was a first direction the connection extended and it was further extended in a first direction by the opposite end of the gate electrode with respect to the contact hole, wherein the this direction of the original ELVDD was in a plane higher intersecting the upper gate electrode 134a of the dual gate electrode structure (Kim Fig. 8; [0097]-[0098]). The second transistor M2 has a first gate electrode connected to the first scan line Si, and a second gate electrode 120, or a back gate or a barrier metal layer, connected and shared with the seventh transistor M7 and its gate occurring on the boundary of the pixel circuit as compared to surrounding pixel circuits PXij (Kim Figs. 1-2; [0030]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Asada in view Arokia and Kim do not teach and is shared by the two sub-pixels.
In the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD), providing mirror symmetry along column axis. Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other, parallel to a base substrate plane such as the base substrate of Asada as modified (Xu Fig. 3; [0032]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Regarding claim 8, Asada in view of Arokia does not teach the display substrate according to claim 1, further comprising an insulating layer between the base substrate and the powerline connection electrode, wherein the powerline connection electrode is electrically connected with the contact hole region through a via hole in the insulating layer.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate and intervening insulating layers 113-114 upon which the data writing/switching transistor M2 was located. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The width of the gate electrode was a first direction the connection extended and it was further extended in a first direction by the opposite end of the gate electrode with respect to the contact hole, wherein the this direction of the original ELVDD was in a plane higher intersecting the upper gate electrode 134a of the dual gate electrode structure (Kim Fig. 8; [0097]-[0098]). It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 9, Asada in view of Arokia does not teach the display substrate according to claim 1, further comprising a first power line extended along the first direction, wherein the first power line is on a side of the powerline connection electrode away from the base substrate and is electrically connected with the powerline connection electrode.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The width of the gate electrode was a first direction the connection extended and it was further extended in a first direction by the opposite end of the gate electrode with respect to the contact hole, wherein the this direction of the original ELVDD was in a plane higher intersecting the upper gate electrode 134a of the dual gate electrode structure (Kim Fig. 8; [0097]-[0098]). It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 12, Asada of the combination of references further teaches the the display substrate according to claim 1, wherein the storage sub-circuit comprises a storage capacitor, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode which respectively serve as the first terminal and a second terminal of the storage sub-circuit (Fig. 16, [0045], a voltage holding second capacitor formed between the gate electrode of the n-type MOS transistor and a first voltage holding capacitor electrode). Asada in view of Arokia does not teach the contact region hole is configured to be electrically connected with the second capacitor electrode of the storage capacitor.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The storage capacitor Cst with two terminals, the second capacitor terminal was connected between the first power supply voltage line ELVDDL and its contact hole, and the first capacitor terminal was connected to node N1 (Kim Fig. 2; [0041]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 13, Asada of the combination of references further teaches the display substrate according to claim 12, wherein the second capacitor electrode is a first region of the base substrate. (Fig. 16, [0045], a voltage holding second capacitor formed between the gate electrode of the n-type MOS transistor and a first voltage holding capacitor electrode). Asada in view of Arokia does not teach the contact region hole is configured to be electrically connected with the second capacitor electrode of the storage capacitor.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The storage capacitor Cst with two terminals, the second capacitor terminal was connected between the first power supply voltage line ELVDDL and its contact hole which connects through the base substrate, and the first capacitor terminal was connected to node N1 (Kim Fig. 2; [0041] and [0098]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 14, Asada in view of Arokia does not teach the display substrate according to claim 13, wherein the first region is in contact with the contact hole region.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The storage capacitor Cst with two terminals, the second capacitor terminal was connected between the first power supply voltage line ELVDDL and its contact hole which connects through the base substrate, and the first capacitor terminal was connected to node N1 (Kim Fig. 2; [0041] and [0098]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 15, Asada in view of Arokia does not teach the display substrate according to claim 13, wherein the contact hole region has a higher doping concentration than the first region While Asada of the combination of references further teaches in Fig. 16, first voltage holding capacitor electrode 105 was in the same layer as p-type lightly doped semiconductor/active layer thin film 404 and [0045], a voltage holding second capacitor formed between the gate electrode of the n-type MOS transistor and a first voltage holding capacitor electrode.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The storage capacitor Cst with two terminals, the second capacitor terminal was connected between the first power supply voltage line ELVDDL and its contact hole which connects through the base substrate, and the first capacitor terminal was connected to node N1 (Kim Fig. 2; [0041] and [0098]). The active layer 131 of the second transistor M2 is doped with boron as described above, the threshold voltage of the second transistor M2 can be positively shifted to reduce an afterimage of the display device 100. The first buffer layer 112 insulates the 2-1-th gate electrode 221 from the active layer 131 of the second transistor M2 was a multilayer structure of silicon nitride (SiNx) and silicon oxide (SiOx) or polysilicon layer. Therefore, the first capacitor electrode and first buffer layer would have been in the same layer as the lightly doped region of the active region and polysilicon layer and overlapping with a lower layer with gate electrode and second capacitor (Kim Figs. 2 and 8; [0076] and [0080]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 16, Asada in view of Arokia does not teach the display substrate according to claim 13, wherein the contact hole region is outside an orthographic projection of the first capacitor on the base substrate.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The storage capacitor Cst with two terminals, the second capacitor terminal was connected between the first power supply voltage line ELVDDL and its contact hole which connects through the base substrate, and the first capacitor terminal was connected to node N1 (Kim Fig. 2; [0041] and [0098]). The active layer 131 of the second transistor M2 is doped with boron as described above, the threshold voltage of the second transistor M2 can be positively shifted to reduce an afterimage of the display device 100. The first buffer layer 112 insulates the 2-1-th gate electrode 221 from the active layer 131 of the second transistor M2 was a multilayer structure of silicon nitride (SiNx) and silicon oxide (SiOx) or polysilicon layer. Therefore, the first capacitor terminal and first buffer layer would have been in the same layer as the lightly doped region of the active region orthographically aligned with M2 away from the second capacitor terminal connected to ELVDDL and its contact hole (Kim Figs. 2 and 8; [0076] and [0080]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 17, Asada in view of Arokia does not teach the display substrate according to claim 12, further comprising a polysilicon layer on a side of the powerline connection electrode close to the base substrate, wherein the first capacitor is in the polysilicon layer and is at least partially overlapped with the second capacitor electrode in a direction perpendicular to the base substrate. While Asada in the combination of references further teaches in Fig. 16, first voltage holding capacitor electrode 105 was in the same layer as p-type lightly doped semiconductor/active layer thin film 404 and [0045], a voltage holding second capacitor formed between the gate electrode of the n-type MOS transistor and a first voltage holding capacitor electrode).
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The active layer 131 of the second transistor M2 is doped with boron as described above, the threshold voltage of the second transistor M2 can be positively shifted to reduce an afterimage of the display device 100. The first buffer layer 112 insulates the 2-1-th gate electrode 221 from the active layer 131 of the second transistor M2 was a multilayer structure of silicon nitride (SiNx) and silicon oxide (SiOx) or polysilicon layer. Therefore, the first capacitor electrode and first buffer layer would have been in the same layer as a doped and polysilicon layer and overlapping with a lower layer with gate electrode and second capacitor (Kim Figs. 2 and 8; [0076] and [0080]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 18, Asada in view of Arokia does not teach the display substrate according to claim 1, wherein base substrate is a silicon substrate, and the contact hole region is a heavily-doped region in the silicon substrate.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The active layer 131 of the second transistor M2 is doped with boron as described above, the threshold voltage of the second transistor M2 can be positively shifted to reduce an afterimage of the display device 100. The first buffer layer 112 of base substrate 111 insulates the 2-1-th gate electrode 221 from the active layer 131 of the second transistor M2 was a multilayer structure of silicon nitride (SiNx) and silicon oxide (SiOx) or polysilicon layer. Therefore, the first capacitor electrode and first buffer layer of the base substrate 111 would have been in the same layer as the lightly doped region of the active region and polysilicon layer as compared to the contact hole with conductive material (Kim Figs. 2 and 8; [0076] and [0080]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 19, Asada of the combination of references further teaches the display device, comprising the display substrate of claim 1 and the light-emitting element (See above and Asada Fig. 2, light emitting element 109 as well as Kim Fig. 2, OLED).
Regarding claim 20, Asada in view Arokia and Kim does not teach the display substrate according to claim 1, wherein the main body portion, the first extension portion and the second first extension portion are in an integral structure.
However, in the analogous art of pixel arrays for OLED devices, Xu teaches that the adjacent two columns of the sub-pixels, wherein the adjacent two columns of the sub-pixels share the same one power line (labeled as VDD). Therefore, the main VDD required a protrusion for the (n+1) sub-pixel circuit and the (n+2) sub-pixel circuit as shown in Fig. 3. The main bodies of VDD extend in the same direction and are parallel with each other (Xu Fig. 3; [0033]-[0035]). It would have been obvious before the effective filing date of the invention to have allowed VDD sharing between pixel lines in the invention of Asada in view Arokia and Kim. One having ordinary skill in the art would have been motivated to have compared with the existing 7T1C circuit, the number of the power lines, the reset signal lines, and the via holes can be reduced by about half in the layout of the present application, thereby providing space for pixels to realize a display device with high PPI (Xu Fig. 3; [0035]).
Claims 6-7 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2006/0232505 A1 by Asada in view of U.S. Patent Publication 2017/0004769 A1 by Arokia, and further in view of U.S. Patent Publication 2020/0243006 A1 by Kim.
Regarding claim 6, Asada teaches the display with a pixel circuit (Fig. 2 was a pixel driving circuit of a display), and the pixel circuit comprises a data writing sub-circuit (Fig. 3, transistor 103), a storage sub-circuit (Fig. 3, storage capacitor CH) and a driving sub-circuit (Fig. 3, transistor 302),
the data writing sub-circuit is electrically connected with a first terminal of the storage sub-circuit (Fig. 3, terminal of transistor Qn connected to a first terminal of capacitor CH), and is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal (Fig. 3, data signal Vd transmitted according to scanning signal 101 to the first terminal of the capacitor CH);
the driving sub-circuit comprises a control electrode (Fig. 3, gate electrode of transistor 302), a first electrode (Fig. 3, terminal of transistor 302 connected to scanning line 101) and a second electrode (Fig. 3, terminal of transistor 302 connected to first terminal of resistor RL), and the control electrode is electrically connected with the first terminal of the storage sub-circuit (Fig. 3, gate electrode of transistor 302 connected to the first terminal of capacitor CH).
However, Asada does not teach display substrate, comprising a base substrate and a sub-pixel on the base substrate, the first electrode of the driving sub-circuit is configured to receive a first power supply voltage, a second terminal of the resistance device is configured to be electrically connected with a first electrode of a light-emitting element, and the driving sub-circuit is configured to drive the light-emitting element to emit light.
Asada provides a resistor provides stability when a voltage shift referred to as feed-through voltage occurs through the capacitance between the gate and source of the transistor (Qn) when the data signal transferred to the pixel electrode 5903 is held by the storage capacitor 5906. In the analogous art of active matrix pixel circuits, Arokia similarly teaches a feedback circuit between a storage capacitor and OLED light emitting display element on a display substrate (Arokia Fig. 1; [0012]). The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels (Arokia [0011]). The feedback circuit comprising a resistor connected between the second terminal of said drive use transistor and a supply potential and provided a voltage is used to adjust the programming voltage of the pixel (Arokia [0010]). It would have been obvious before the effective filing date of the invention to have switched the liquid crystal with the light emitting element and driving transistor providing a current. As current through OLED strongly depends on the characteristic parameters of the driving and programming TFT. Since the characteristic parameters of a TFT, particularly, the threshold voltage under bias stress, vary by time, and such changes may differ from pixel to pixel, the induced image distortion may be unacceptably high. The programming voltage can be accurately adjusted by an external control unit through the use of feedback voltage generated by the on-pixel feedback circuit. The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current by the driving transistor despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels. One of the methods that has been employed to make the current driving circuit less sensitive to the shift in the threshold voltage is programming the pixel with current instead of voltage (Arokia Fig. 1; [0010]-[0011] and [0007]).
Asada in view of Arokia does not teach:
the base substrate comprises a contact hole region configured to provide a power voltage to the pixel circuit, and the display substrate further comprises a powerline connection electrode electrically connected to the contact hole region;
the powerline connection electrode comprises a main body portion, and a first extension portion and a second first extension portion extended from the main body portion; and first extension portion and the second extension portion are both extended along a first direction, the main body portion is extended along a second direction, and the first direction intersects the second direction.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a second gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The width of the gate electrode was a first direction the connection extended and it was further extended in a first direction by the opposite end of the gate electrode with respect to the contact hole, wherein the this direction of the original ELVDD was in a plane higher intersecting the upper gate electrode 134a of the dual gate electrode structure (Kim Fig. 8; [0097]-[0098]). It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Asada in view of Arokia does not teach wherein the powerline connection electrode is between two sub-pixels adjacent in the first direction and is shared by the two sub-pixels (Applicant in Specification paragraph [00214]-[00219] describes cross-shaped connection electrode 325 as connected to the contact hole region in the base substrate and alternately distributed in a first direction D1 and was located at a boundary of sub-pixel rows. A connection electrode 324 or 325 was provided between every two data line connection portions arranged at intervals in the first direction. While two sub-pixels adjacent in the second direction could share one data line connection portion, however these were data connection portions and also in the second direction but not the first direction where connection electrode 325 was oriented. Therefore, for the purposes of examination, the connection electrode located at a boundary of two pixels is shared by two sub-pixels.)
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The contact hole was a first direction the connection extended in a second direction perpendicular in both directions with respect to the contact hole (Kim Fig. 8; [0097]-[0098]). The second transistor M2 has a first gate electrode connected to the first scan line Si, and a second gate electrode 120, or a back gate or a barrier metal layer, connected and shared with the seventh transistor M7 and its gate occurring on the boundary of the pixel circuit as compared to surrounding pixel circuits PXij (Kim Figs. 1-2; [0030]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 7, Asada in view of Arokia does not teach the display substrate according to claim 6, wherein the first extension portion and the second extension portion respectively extend from the main body portion towards the two sub-pixels, and are respectively overlapped a corresponding sub-pixel.
transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The contact hole was a first direction the connection extended in a second direction perpendicular in both directions with respect to the contact hole (Kim Fig. 8; [0097]-[0098]). The second transistor M2 has a first gate electrode connected to the first scan line Si, and a second gate electrode 120, or a back gate or a barrier metal layer, connected and shared with the seventh transistor M7 and its gate occurring on the boundary of the overlapping pixel circuit as compared to surrounding pixel circuits PXij in the first direction (Kim Figs. 1-2; [0030]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Regarding claim 10, Asada teaches the display with a pixel circuit (Fig. 2 was a pixel driving circuit of a display), and the pixel circuit comprises a data writing sub-circuit (Fig. 3, transistor 103), a storage sub-circuit (Fig. 3, storage capacitor CH) and a driving sub-circuit (Fig. 3, transistor 302),
the data writing sub-circuit is electrically connected with a first terminal of the storage sub-circuit (Fig. 3, terminal of transistor Qn connected to a first terminal of capacitor CH), and is configured to transmit a data signal to the first terminal of the storage sub-circuit in response to a control signal (Fig. 3, data signal Vd transmitted according to scanning signal 101 to the first terminal of the capacitor CH);
the driving sub-circuit comprises a control electrode (Fig. 3, gate electrode of transistor 302), a first electrode (Fig. 3, terminal of transistor 302 connected to scanning line 101) and a second electrode (Fig. 3, terminal of transistor 302 connected to first terminal of resistor RL), and the control electrode is electrically connected with the first terminal of the storage sub-circuit (Fig. 3, gate electrode of transistor 302 connected to the first terminal of capacitor CH).
However, Asada does not teach display substrate, comprising a base substrate and a sub-pixel on the base substrate, the first electrode of the driving sub-circuit is configured to receive a first power supply voltage, a second terminal of the resistance device is configured to be electrically connected with a first electrode of a light-emitting element, and the driving sub-circuit is configured to drive the light-emitting element to emit light.
Asada provides a resistor provides stability when a voltage shift referred to as feed-through voltage occurs through the capacitance between the gate and source of the transistor (Qn) when the data signal transferred to the pixel electrode 5903 is held by the storage capacitor 5906. In the analogous art of active matrix pixel circuits, Arokia similarly teaches a feedback circuit between a storage capacitor and OLED light emitting display element on a display substrate (Arokia Fig. 1; [0012]). The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels (Arokia [0011]). The feedback circuit comprising a resistor connected between the second terminal of said drive use transistor and a supply potential and provided a voltage is used to adjust the programming voltage of the pixel (Arokia [0010]). It would have been obvious before the effective filing date of the invention to have switched the liquid crystal with the light emitting element and driving transistor providing a current. As current through OLED strongly depends on the characteristic parameters of the driving and programming TFT. Since the characteristic parameters of a TFT, particularly, the threshold voltage under bias stress, vary by time, and such changes may differ from pixel to pixel, the induced image distortion may be unacceptably high. The programming voltage can be accurately adjusted by an external control unit through the use of feedback voltage generated by the on-pixel feedback circuit. The feedback voltage is proportional to the driving current of the light emitting element and is used to set the programming voltage so as to achieve the desired driving current by the driving transistor despite presence of any instability (shift in characteristics of transistors and light emitting element) and non-uniformity across pixels. One of the methods that has been employed to make the current driving circuit less sensitive to the shift in the threshold voltage is programming the pixel with current instead of voltage (Arokia Fig. 1; [0010]-[0011] and [0007]).
Asada in view of Arokia does not teach:
the base substrate comprises a contact hole region configured to provide a power voltage to the pixel circuit, and the display substrate further comprises a powerline connection electrode electrically connected to the contact hole region;
the powerline connection electrode comprises a main body portion, and a first extension portion and a second first extension portion extended from the main body portion; and first extension portion and the second extension portion are both extended along a first direction, the main body portion is extended along a second direction, and the first direction intersects the second direction,
a second power line extended along the second direction, wherein the second power line is on a side of the first power line away from the base substrate and is electrically connected with the first power line.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a second gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The contact hole was a first direction the connection extended in a second direction perpendicular in both directions with respect to the contact hole (Kim Fig. 8; [0097]-[0098]). It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
0Regarding claim 11, Asada in view of Arokia does not teach the display substrate according to claim 10, further comprising a third power line extended along the second direction, wherein the third power line is overlapped with the second power line in a direction perpendicular to the base substrate and is electrically connected with the second power line.
However, in the analogous art of pixel circuits controlled by current to a driving transistor for a display device, Kim teaches a connection electrode to a power supply voltage ELVDD that was provided by a first power supply voltage line ELVDD (Kim Fig. 1; [0004]-[0006]; Abstract). The power supply voltage ELVDD was electrically connected to a gate electrode 422 under a data writing transistor M2. A contact hole with conductive material connected the power supply voltage ELVDD with the gate electrode and was formed through a base substrate upon which the data writing/switching transistor M2 was located. The contact hole was a first direction the connection extended and it was further extended in a second direction perpendicular in both opposite directions with respect to the contact hole in a single pixel circuit but also continued in the second direction beyond the extensions to other pixel circuits (Kim Fig. 8; [0097]-[0098]). An emission supply line Ei arranged in the second direction away from base substrate 111 and was electrically connected to the first power supply voltage line ELVDD (Kim Fig. 2 and Fig. 8; [0048]).0074, When Ei was electrical connection was cut off, a current path is created that connects the first power supply voltage line ELVDDL, the fifth transistor M5, the first transistor M1, the sixth transistor M6, the organic light emitting diode OLED, and the second power supply voltage line ELVSSL going through active layers and gate layers perpendicular to the base substrate (Kim Fig. 2 and Fig. 8; [0074]).
It would have been obvious before the effective filing date of the invention to have gate electrode 422 electrically connected to the first power supply voltage line ELVDDL, and high level first power supply voltage can be continuously transmitted during each image frame. Therefore, the threshold voltage of the second transistor M2 was more effectively negatively shifted. Accordingly, an afterimage of the display device 300 was reduced, and generation of horizontal stripes can be more effectively reduced even when the display device 300 was used for a long period of time or at a high temperature (Kim Fig. 8; [0097]-[0098]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/MAHEEN I JAVED/Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621