DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 1 is objected to because of the following informalities: in line 7 of the claim, “disposed one” appears to be a typographical error that should be corrected to ‘disposed on’.
Claim 8 is objected to because of the following informalities: the drafting of the first instance of the acronym “TSV” should be spelled out.
Claim 14 is objected to because of the following informalities: in line 3 of the claim, “and opposite” appears to be a typographical error that should be corrected to ‘an opposite’.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chi et al. (US Pub. No. 2013/0106463), hereinafter referred to as Chi, in view of Siers et al. (US Pub. No. 2023/0205094), hereinafter referred to as Siers, further in view of Gao et al. (US Pub. No. 2023/0187412), hereinafter referred to as Gao.
Referring to claim 1, Chi discloses an integrated circuit (IC) die stack (fig. 1B, fig. 7), comprising: at least one memory layer (fig. 1B, 100b, functional circuitry 110 is a circuit block, for example memory, [0018]); a digital device die (fig. 1B, 110a, functional circuitry 110 is…logic circuitries, 0018]); and at least one bypass chiplet (fig. 7, bypass the die 700a, [0037]) disposed adjacent the digital device die in a common layer, the at least one memory layer disposed on the at least one bypass chiplet (Fig. 7 depicts the programmable array 120 adjacent to 110 functional circuitry 110a, and the 700b layer is disposed on the 700a layer, 700b layer includes functional circuitry 110b which is disclosed as a memory layer, [0018]), wherein the at least one memory layer is on a first side of the digital device and the at least one bypass chiplet (fig. 1B, fig. 7, stack arrangement), and signals pass through the at least one bypass chiplet to the at least one memory layer (bypass the die 700a, [0037]).
While Chi teaches memory, Chi is silent regarding a memory controller and therefore does not appear to explicitly disclose at least one memory controller disposed outside of the digital device die and connected to the at least one memory layer. As well, while Chi discusses power considerations, Chi is silent regarding the passing of power.
However, Siers discloses at least one memory controller disposed outside of the digital device die and connected to the at least one memory layer (Memory PHY chiplets 605, 606 provide interface and controls for memory components 601, 602. Memory PHY chiplets 605, 606 may also be characterized as memory controllers, [0048])
Furthermore, Gao discloses a power providing path (see, [0011]).
Chi, Siers, and Gao are analogous art because they are from the same field of endeavor, IC architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to modify the IC interconnect architecture of Chi to include the memory controller of Seirs and the power distribution of Gao because the memory controllers would provide interfacing and control of the memory components and architecture would reduce power consumption.
The suggestion/motivation for doing so would have been to provide memory control and interface component (Siers: [0048]) and reduce power consumption (Gao: [0018])
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 2, while Chi teaches a substrate coupled to the digital device die and the at least one bypass chiplet, wherein the substrate is on a second side of the digital device and the at least one bypass chiplet (fig. 1, 3, and 7; substrate 190/290/790), Chi does not appear to explicitly disclose the substrate as an interposer.
However, Gao discloses an interposer (a stack of multiple integrated device dies 1 mounted to a carrier 2, such as another large die, interposer, base device or package substrate, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to substitute the substrate of Chi to with the interposer taught by Gao because the prior art of Chi contained a device which differed from the claimed device by the substitution of an anticipated substrate with a specific interposer component; Goa demonstrates that the substituted interposer and its functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable stack architecture.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 3, the combination of Chi, Siers, and Gao teaches the at least one memory controller is electrically coupled to the at least one memory layer through the at least one bypass chiplet (Chi: bypass the die 700a, [0037]; Siers: a complete pass through connection is provided from memory PHY chiplet 605 to embedded interconnect bridge 631 and then to memory component 601, [0049]). The suggestion/motivation to combine remains as indicated above.
As to claim 4, while Chi discloses the substrate comprises a data fabric (fig. 1-7) /
However, Gao discloses an interposer (a stack of multiple integrated device dies 1 mounted to a carrier 2, such as another large die, interposer, base device or package substrate, [0018]).
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 5, Chi does not appear to explicitly disclose at least one memory controller is disposed in the least one bypass chiplet and electrically coupled to the at least one memory layer.
However, Siers discloses at least one memory controller is disposed in the least one bypass chiplet and electrically coupled to the at least one memory layer (fig. 7, PHY+MC combination 605/606, electrically connected to MEM).
The suggestion/motivation to combine remains as indicated above with respect to the memory controller.
As to claim 6, Chi discloses the at least one memory layer is a plurality of memory layers forming a memory stack (fig. 1B, 3, 7).
As to claim 7, the combination of Chi, Siers, and Gao disclose a passive silicon structure thermally coupled to the digital device die, the passive silicon structure disposed laterally adjacent to the at least one memory layer (Chi: electrical connection 114, 114', 116 and 116'…electrical connection 112 may be any form of interconnection, such as metal, via, TSVs, or any conductor made of other materials, [0017-0018], NOTE: in the stack configuration the connections are “disposed laterally adjacent” to the memory layers; Goa: TSVs 29 can additionally serve to carry power, ground or signals if they connect thermally, [0031]; (TSVs), such as through silicon vias, [0037]).
As to claim 8, while Chi teaches the digital device die overlaps the at least one memory layer and does not have TSV passing therethrough (fig. 7, the functional circuitry 110a of layer 700a is under the 700b layer, and therefore overlapped, and there are not TSVs passing therethrough functional circuitry 110a).
As to claim 9, while Chi discloses a package substrate electrically coupled and adapted for electrically coupling the interposer to printed circuit board connections (substrate 190 may be a printed circuit board, [0021]), Chi does not appear to explicitly disclose the substrate as an interposer.
However, Gao discloses an interposer (a stack of multiple integrated device dies 1 mounted to a carrier 2, such as another large die, interposer, base device or package substrate, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to substitute the substrate of Chi to with the interposer taught by Gao because the prior art of Chi contained a device which differed from the claimed device by the substitution of an anticipated substrate with a specific interposer component; Goa demonstrates that the substituted interposer and its functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable stack architecture.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 10, Chi discloses the digital device die is selected from the group consisting of any one or a combination of a microcontroller, a microprocessor (functional circuitry 110 is a...general processor, [0018]), a mixed signal processor, a central processing unit (CPU), a programmable logic array (PLA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU) (functional circuitry 110 is a...graphic processor, [0018]), a field programmable gate array (FPGA), neural processing unit and tensor processing unit.
As to claim 11, while Chi discloses the at least one memory layer, Chi is silent regarding the specific type of memory and therefore does not appear to explicitly disclose the type is selected from the group consisting of dynamic random-access memory (DRAM), static random-access memory (SRAM), serial shift registers, eDRAM, Flash, phase-change memory, resistive RAM, ferromagnetic RAM and spin-torque transfer RAM.
However, Gao discloses high bandwidth memory (HBM), which is a type of dynamic random-access memory (DRAM) (see [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to substitute the memory type anticipated by Chi to with the DRAM type memory taught by Gao because the prior art of Chi contained a device which differed from the claimed device by the substitution of an anticipated memory type with a specific DRAM type memory; Goa demonstrates that the substituted memory type and its functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable memory stack.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 12, the combination of Chi, Siers, and Gao discloses the cooling solution is a thermal dissipation device with heat transfer enhancement structures selected from the group consisting of a heat sink (Gao: overlying element can be heat sink 28, which can be directly …TSVs can aid in heat extraction to the heat sink 2, [0031]), a heat sink with fins, liquid cooling tubes, vapor chambers, heat pipes, cold plates.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to modify the IC interconnect architecture of Chi to include the heat sink of Gao because the prior art of and Gao included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference; one of ordinary skill in the art could have combined the stack coupling and heat sink elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately; and one of ordinary skill in the art would have recognized that the results of the combination were predictable memory stack architecture with heat extraction functionality. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395 (see MPEP 2143.I.A) Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
Referring to claim 13, Chi discloses an integrated circuit (IC) die stack (fig. 1B, fig. 7), comprising: a first at least one memory layer (fig. 7, 700c; functional circuitry 110 is a circuit block, for example memory, [0018]); a second at least one memory layer (fig. 7, 700d, functional circuitry 110 is a circuit block, for example memory, [0018]); a digital device die (fig. 7, 110a, functional circuitry 110 is…logic circuitries, 0018]); and at least two bypass chiplets (fig. 1B, fig. 7; bypass the die 700a, [0037]; bypass the die 700b…bypass the die 700c, [0038]), wherein at least one of the first and second at least one memory layers overlap digital device die and at least one of the he at least two bypass chiplets (fig. 1B, fig. 7, stack arrangement; fig. 7, the functional circuitry 110a of layer 700a is under the 700b layer, and therefore overlapped), and signals pass through at least one of the at least two bypass chiplets to the first and second at least one memory layers (fig. 1B, fig. 7; bypass the die 700a, [0037]; bypass the die 700b…bypass the die 700c, [0038]).
While Chi teaches the at least two bypass chiplets and depicts one bypass chiplet adjacent to the digital device in a common layer, Chi does not appear to explicitly disclose an architecture in which the at least two bypass chiplets are in the common layer. As well, while Chi discusses power considerations, Chi is silent regarding the passing of power.
However, Siers discloses an architecture in which the at least two bypass chiplets are in the common layer (Fig. 6, EMIBs 631 and 632 in common layer; a complete pass through connection is provided from memory PHY chiplet 605 to embedded interconnect bridge 631 and then to memory component 601, [0049]).
Furthermore, Gao discloses a power providing path (see, [0011]).
Chi, Siers, and Gao are analogous art because they are from the same field of endeavor, IC architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to modify the IC interconnect architecture of Chi to include dual bridge architecture of Siers and the power distribution of Gao because the dual bridge architecture would provide control and interfacing to separate memory components and the power architecture would reduce power consumption.
The suggestion/motivation for doing so would have been to provide additional memory control and interfacing (Siers: [0048]) and reduce power consumption (Gao: [0018])
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 14, while Chi teaches a substrate coupled to the digital device die and the at least two bypass chiplets, wherein the substrate is on an opposite side of the digital device die relative to the first and second at least on memory layers (fig. 1, 3, and 7; substrate 190/290/790 is below functional circuitry 110a while the memory layers 250 and 260 are above the functional circuitry 110a), Chi does not appear to explicitly disclose the substrate as an interposer.
However, Gao discloses an interposer (a stack of multiple integrated device dies 1 mounted to a carrier 2, such as another large die, interposer, base device or package substrate, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Siers, and Gao before him or her, to substitute the substrate of Chi to with the interposer taught by Gao because the prior art of Chi contained a device which differed from the claimed device by the substitution of an anticipated substrate with a specific interposer component; Goa demonstrates that the substituted interposer and its functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable stack architecture.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi, Siers, and Gao to obtain the invention as specified in the instant claim.
As to claim 15, while Chi teaches at least two components electrically coupled to respective ones of the first and second at least one memory layers through the at least two bypass chiplets and Gao teaches the interposer, the combination of Chi in view of Gao does not appear to explicitly disclose the at least two components being memory controllers.
However, Siers discloses at least two memory controllers electrically coupled to respective ones of the first and second at least one memory layers through the at least two bypass chiplets (Memory PHY chiplets 605, 606 provide interface and controls for memory components 601, 602. Memory PHY chiplets 605, 606 may also be characterized as memory controllers…a complete pass through connection is provided from memory PHY chiplet 605 to embedded interconnect bridge 631 and then to memory component 601, [0048-0049]).
The suggestion/motivation to combine remains as indicated above with respect to the memory controller.
As to claim 16, Chi does not appear to explicitly disclose each of the at least two bypass chiplets comprises at least one memory controller electrically coupled to a respective one of the first and second at least one memory layers.
However, Siers discloses each of the at least two bypass chiplets comprises at least one memory controller electrically coupled to a respective one of the first and second at least one memory layers (fig. 7, PHY+MC combination 605/606, electrically connected to MEM).
The suggestion/motivation to combine remains as indicated above with respect to the memory controller.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Gao
Referring to claim 17, Chi discloses an integrated circuit (IC) die stack (fig. 1B, fig. 7), comprising: a first at least one memory layer (fig. 7, 700c; functional circuitry 110 is a circuit block, for example memory, [0018]); a second at least one memory layer (fig. 7, 700d, functional circuitry 110 is a circuit block, for example memory, [0018]); a digital device die (fig. 1B, 110a, functional circuitry 110 is…logic circuitries, 0018]); and at least one bypass chiplet (fig. 1B, fig. 7; bypass the die 700a, [0037]; bypass the die 700b…bypass the die 700c, [0038]) disposed adjacent the digital device die in a common layer (Fig. 7 depicts the programmable array 120 of 700a adjacent to functional circuitry 110a in the common layer of 700a), wherein the first and second at least one memory layers are on a first side of the digital device die and the at least one bypass chiplets (fig. fig. 7, stack arrangement), and wherein signals pass through the at least one bypass chiplet to respective ones of the first and second at least one memory layers (fig. 1B, fig. 7; bypass the die 700a, [0037]; bypass the die 700b…bypass the die 700c, [0038]), wherein the first and second at least one memory layer receive power not from the digital device die (power consumption requirement of the die stack. The stacked redundant dies in a die stack… redundant die contains a higher volume of memory, [0039-0042]; NOTE: the functional circuitry is not described as a power supply unit, therefore the power being consumed by the die stack is “not from the digital device die”).
While Chi discusses power considerations, Chi is silent regarding the passing of power.
However, Gao discloses a power providing path (see, [0011]).
Chi and Gao are analogous art because they are from the same field of endeavor, IC architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi and Gao before him or her, to modify the IC interconnect architecture of Chi to include the power distribution of Gao because the architecture would reduce power consumption.
The suggestion/motivation for doing so would have been to reduce power consumption (Gao: [0018])
Therefore, it would have been obvious to combine Chi and Gao to obtain the invention as specified in the instant claim.
As to claim 18, while Chi teaches a substrate coupled to the digital device die and the at least one bypass chiplet, wherein the substrate is on a second side of the digital device die and the at least one bypass chiplet (fig. 1, 3, and 7; substrate 190/290/790), Chi does not appear to explicitly disclose the substrate as an interposer.
However, Gao discloses an interposer (a stack of multiple integrated device dies 1 mounted to a carrier 2, such as another large die, interposer, base device or package substrate, [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi and Gao before him or her, to substitute the substrate of Chi to with the interposer taught by Gao because the prior art of Chi contained a device which differed from the claimed device by the substitution of an anticipated substrate with a specific interposer component; Goa demonstrates that the substituted interposer and its functions were known in the art; and one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable stack architecture.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143.I.B).
Therefore, it would have been obvious to combine Chi and Gao to obtain the invention as specified in the instant claim.
Claim 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chi in view of Gao, as applied to claims 17-18 above, further in view of Siers.
As to claim 19, while Chi teaches at least two components electrically coupled to respective ones of the first and second at least one memory layers through the at least one bypass chiplet and Gao teaches the interposer, the combination of Chi in view of Gao does not appear to explicitly disclose the at least two components being memory controllers.
However, Siers discloses at least two memory controllers (Memory PHY chiplets 605, 606 provide interface and controls for memory components 601, 602. Memory PHY chiplets 605, 606 may also be characterized as memory controllers, [0048-0049]).
The suggestion/motivation remains as indicated above with respect to the memory controller.
Chi, Gao, and Siers are analogous art because they are from the same field of endeavor, IC architecture.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chi, Gao, and Siers before him or her, to modify the IC interconnect architecture of Chi to include the memory controller of Seirs because the memory controllers would provide interfacing and control of the memory components.
The suggestion/motivation for doing so would have been to provide memory control and interface component (Siers: [0048]).
Therefore, it would have been obvious to combine Chi, Gao, and Siers to obtain the invention as specified in the instant claim.
As to claim 20, Chi does not appear to explicitly disclose the at least one bypass chiplet comprises at least two memory controllers electrically coupled to a respective one of the first and second at least one memory layers.
However, Siers discloses each of the at least one bypass chiplet comprises at least two memory controllers electrically coupled to a respective one of the first and second at least one memory layers (fig. 7, PHY+MC combination 605/606, electrically connected to MEMs).
The suggestion/motivation to combine remains as indicated above with respect to the memory controller.
Response to Arguments
Applicant's arguments filed 6/10/2026 have been fully considered but they are not persuasive. Regarding the teachings of Chi in view of the amendments the Applicant asserts “In contrast, each and every IC die in Chi are vertically stacked one on top of the other such that no two dies reside in a common layer.” The Examiner respectfully disagrees; as demonstrated by the revised rejections above, the programmable array and the functional circuitry are in a common layer of the stacked layers. The Applicant’s remarks regarding the memory controller amendments are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. For more information about the Patent Center, see https://patentcenter.uspto.gov/. Should you have questions on access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
Prosecution Insights