DETAILED ACTION
This Office action is in response to the application filed on December 14, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 14, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on December 14, 2023. These drawings are accepted by the Examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-12, 15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singnurkar (U.S. Pat. No. 9,035,638 B2, reference provided as part of the Information Disclosure Statement “IDS”).
In re claim 1, Singnurkar discloses a DC-DC converter (Fig. 1A) comprising:
a voltage converter (11) configured to receive an input voltage (VIN) through an input node (10), to convert the input voltage into an output voltage (VOUT), and to output the output voltage to an output node (output node of 11); and
a controller (controller circuitry) configured to select at least one conversion manner among a plurality of conversion manners (the controller can select between operating in a buck (MODEBU), boost (MODEBO), or buck-boost mode (MODEBB)) with the selection based on a first ratio of a charging period of one cycle, to charge internal elements (L and capacitor 15) in the at least one conversion manner during the charging period of the one cycle, and to control the voltage converter to discharge the internal elements in the at least one conversion manner during a discharging period of the one cycle (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15).
In re claim 2, Singnurkar discloses (Fig. 1A) wherein the plurality of conversion manners include a buck conversion manner, a buck-boost conversion manner, and a boost conversion manner (the controller can select between operating in a buck (MODEBU), boost (MODEBO), or buck-boost mode (MODEBB)).
In re claim 3, Singnurkar discloses wherein the controller is configured to sequentially select the buck conversion manner, the buck-boost conversion manner, and the boost conversion manner based on the first ratio, during the charging period (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15).
In re claim 4, Singnurkar discloses (Fig. 1A) wherein the controller is configured to determine a timing to start the discharging period, based on a level of an error voltage corresponding to a difference between the output voltage and a target voltage of the output voltage (Col. 4 lines 35-67, Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12).
In re claim 10, Singnurkar discloses (Fig. 1A) wherein the controller is configured to: receive a reference clock signal corresponding to the one cycle (Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12); and allow the voltage converter to start a boost conversion manner among the plurality of conversion manners in synchronization with the reference clock signal in the charging period (Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12).
In re claim 11, Singnurkar discloses (Fig. 1A) wherein the controller is configured to: generate a first clock signal by delaying the reference clock signal as much as a first delay value (Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12); and enable the voltage converter to halt a buck conversion manner among the plurality of conversion manners in synchronization with the first clock signal in the charging period (Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12).
In re claim 12, Singnurkar discloses (Fig. 1A) wherein, in the charging period, the controller is configured to enable the voltage converter to perform a buck-boost conversion manner among the plurality of conversion manners during a time period corresponding to the first delay value (Col. 5 lines 1-35 and 53-67, Col. 6 lines 1-12).
In re claim 15, Singnurkar discloses a DC-DC converter (Fig. 1A) comprising:
a voltage converter (11) configured to receive an input voltage (VIN) through an input node (10), to convert the input voltage into an output voltage (VOUT), and to output the output voltage to an output node (output node of 11); and
a controller (control circuitry) configured to charge internal elements (L and capacitor 15) during a charging period of one cycle and to control the voltage converter to discharge the internal elements during a discharging period of the one cycle, wherein the controller is configured to adjust a timing to reset the one cycle based on the input voltage and the output voltage (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15).
In re claim 20, Singnurkar discloses an operating method of a DC-DC converter (Fig. 1A) configured to convert an input voltage (VIN) into an output voltage (VOUT), the method comprising:
performing charging of internal elements (L and capacitor 15) while changing a voltage conversion manner (the converter 11 can operate between a buck (MODEBU), boost (MODEBO), or buck-boost mode (MODEBB)) over time, the performing the charging of internal elements being in a charging period of one cycle (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15);
performing discharging of the internal elements (L and capacitor 15) based on a last voltage conversion manner of the charging period, the performing the discharging of the internal elements being in a discharging period of the one cycle (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15); and
resetting the one cycle based on the input voltage and the output voltage (Fig. 3B, Col. 11, lines 1-15 and Col. 12, lines 1-15).
Allowable Subject Matter
Claims 5-9, 13-14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 5, the prior art of record fails to disclose or suggest “wherein the controller is configured to adjust a timing to reset the one cycle based on the input voltage and the output voltage” in combination with other limitations of the claim. Claims 6-9 depend directly or indirectly from claim 5 and are, therefore, also objected at least for the same for the reasons set above.
Regarding to claim 13, the prior art of record fails to disclose or suggest “wherein the controller is configured to: generate a second clock signal by delaying the reference clock signal as much as a second delay value; and reset the one cycle in synchronization with the second clock signal” in combination with other limitations of the claim. Claim 14 depends directly from claim 13 and is, therefore, also objected at least for the same for the reasons set above.
Regarding to claim 16, the prior art of record fails to disclose or suggest “wherein the controller is configured to advance the timing to reset the one cycle as a ratio of the output voltage to the input voltage decreases” in combination with other limitations of the claim. Claim 17 depends directly from claim 16 and is, therefore, also objected at least for the same for the reasons set above.
Regarding to claim 18, the prior art of record fails to disclose or suggest “wherein the controller is configured to delay the timing to reset the one cycle as a ratio of the output voltage to the input voltage increases” in combination with other limitations of the claim. Claim 19 depends directly from claim 18 and is, therefore, also objected at least for the same for the reasons set above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838