DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyake (US 9,236,876 B2).
Regarding claim 1, Miyake discloses an A/D converter (100; fig. 1) comprising: an integrating circuit (10) including: an amplifier (11) including a first input end (connected to R1) and a second input end connected to an application end of a first reference voltage (Vref2); a capacitor (C) connecting the first input end (connected to R1) of the amplifier (11) and an output end (connected to V0) of the amplifier (11); a first resistor (R1) connected between an application end of an input voltage (Vin) and the first input end of the amplifier (11); a first switch (SW1) connected between the application end of the input voltage (Vin) and the first input end of the amplifier (11); a second resistor (R2) connected between an application end of a second reference voltage (Vref1) and the first input end of the amplifier (11); and a second switch (SW2) connected between the application end of the second reference voltage (Vref1) and the first input end of the amplifier (11); a first comparator (30) including a first input end connected to the output end (V0) of the amplifier (11) and a second input end connected to the application end of the first reference voltage (Vref2); and a switch controller (40) configured to control the first switch (SW1) and the second switch (SW2), wherein the switch controller (40) is configured to switch the first switch (SW1) to an off state and switch the second switch (SW2) to an on state upon detecting that an output voltage (V0) of the amplifier (11) has reached a third reference voltage (minimum voltage of V01; fig. 2A-2C) until a predetermined period (T31) has elapsed after turning on the first switch (SW1) and turning off the second switch (SW2) or when the predetermined period (T31) has elapsed without the output voltage of the amplifier reaching the third reference voltage (control circuit 40 switches SW1 to an OFF-state and SW2 to an ON-state when output voltage V0 of amplifier 11 has reached a minimum voltage or until a predetermined period T has elapsed; figs. 2A-2C and c. 5, ll. 12-17).
Regarding claim 4, Miyake discloses further comprising: a counter (42; fig. 1) configured to count a charging period count value corresponding to a charging period until the output voltage (V0) reaches the third reference voltage after turning on the first switch (SW1) and turning off the second switch (SW2) and count a discharging period count value corresponding to a discharging period until the output voltage (V0) reaches the first reference voltage after turning off the first switch (SW1) and turning on the second switch (when is SW1 is ON, capacitor C is charged, and when SW1 is OFF and SW3 is ON, capacitor C is discharged therefore, counter 42 counts a charging integration period after turning ON SW1 and counts a discharging integration period until V0 reaches Vref2 after switch SW1 is turned OFF; figs. 2A-2D and c. 3, ll. 26-28 and c. 4, ll. 13-25), wherein an output value (Vout) based on the charging period count value is set as an output of the A/D converter (100) upon detecting that the output voltage (V0) has reached the third reference voltage until the predetermined period (T31) has elapsed after turning on the first switch (SW1) and turning off the second switch (output value Vout based on the charging integration period is set as an output of A/D converter 100 upon detecting that output voltage V0 has reached a minimum voltage until period T31 has elapsed after SW1 is turned on and SW2 is turned OFF; c. 4, ll. 19-25), and wherein a logic circuit (43) sets the discharging period count value as the output (Vout) of the A/D converter (100) when the predetermined period has elapsed without the output voltage reaching the third reference voltage (A/D control circuit 43 sets the discharging integration period count value as output Vout of A/D converter 100 when period T31 has elapsed; c. 4, ll. 13-25).
Regarding claim 8, Miyake discloses a sensor apparatus (detection circuit) comprising: the A/D converter (100); and a resistance bridge circuit (Wheatstone bridge circuit) provided before the A/D converter (c. 1, ll. 43-47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 9,236,876 B2).
Regarding claim 6, Miyake discloses wherein the first resistor (R1) and the second resistor (R2) have a same resistance value (values of resistors R1 and R2 may be the same; c. 3, ll. 40-41).
Miyake is silent on the first reference voltage being ground potential.
However, one of ordinary skill in the art would have known that a reference voltage in an amplifier circuit may be set to ground and this is applying a known technique to a known device.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the apparatus of Miyake to provide the first reference voltage as a ground potential as this is applying a known technique to a known device to yield predictable results.
Regarding claim 7, Miyake is silent on the first resistor and second resistor being a common resistor.
However, as both resistors (R1 and R2) may be the same value and are connected to the amplifier (11) via switches (SW1 and SW2), one of ordinary skill in the art would have conceived of using a single common resistor.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the apparatus of Miyake to use a single common resistor to reduce the number of parts and simplify the circuit.
Allowable Subject Matter
Claims 2, 3, and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not disclose or suggest “a second comparator configured to compare the output voltage and the third reference voltage and output a comparison result to the switch controller” in combination with the remaining claim elements as recited in claims 2 and 3.
The prior art does not disclose or suggest “wherein the output value based on the charging period count value is CNT2/CNT1, where CNT1 is the charging period count value and CNT2 is the discharging period count value” in combination with the remaining claim elements as recited in claim 5.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erika J. Villaluna whose telephone number is (571)272-8348. The examiner can normally be reached Mon-Fri 9:00 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephanie Bloss can be reached at (571) 272-3555. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIKA J. VILLALUNA/Primary Examiner, Art Unit 2852