Prosecution Insights
Last updated: October 27, 2026
Application No. 18/540,372

DISPLAY DEVICE

Final Rejection §103§112
Filed
Dec 14, 2023
Priority
Jan 26, 2023 — RE 10-2023-0010406
Examiner
RAMOS-DIAZ, FERNANDO JOSE
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
16 granted / 20 resolved
+12.0% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
33 currently pending
Career history
66
Total Applications
across all art units

Statute-Specific Performance

§103
45.7%
+5.7% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 20 resolved cases

Office Action

§103 §112
DETAILED ACTION/EXAMINER’S COMMENT This Office action responds to the amendments filed on 07/01/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status Applicant’s response filed on 07/01/2026 in reply to the non-final rejection mailed on 04/01/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 19 & 20 are added. Accordingly, pending in this Office action are claims 1-20. Claim Rejections – 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitations “a black bank layer protrusion… so as to form a protrusion positioned in the slit or through hole” and “the protrusion of black bank layer” in lines 7-8 & 11, respectively. There is insufficient antecedent basis for “the protrusion of black bank layer” in the claim. In addition, Claims 2, 10-13 & 19 recite different variations of the limitation such as “the protrusion of the black bank layer,” “the protrusion of black bank layer,” and “the protrusion” and incorporate the same issue. The consistency of the limitation is unclear and consistent claim language is suggested to particularly point out and distinctly claim the subject. Claims 2-20 are rejected as depending on Claim 1. Similarly to Claim 1, Claim 13 recites the limitations “wherein the color filter layer includes a slit or through hole formed in an upper portion of the color filter layer” & “the slit or through hole of the color filter layer” in lines 1-3. There is insufficient antecedent basis for “the slit or through hole of the color filter layer” in the claim. Regarding Claim 17, the limitation “a gate electrode disposed over a portion of the semiconductor layer where the emission area is positioned” does not particularly point out and distinctly claim the subject matter of the invention shown in the application. The specification (see, e.g., para.0055, para.0059) defines the emission area EA as the opening OPH of the black bank layer BB. The area of the substrate where the black bank layer BB is positioned is defined as the non-emission area NEA. Figs. 6-9 of the drawings shows the semiconductor layer having portions positioned in the opening, the emission area and the non-emission area. However, these figures show the gate electrode GA is disposed over a portion of the semiconductor layer where the non-emission area NEA is positioned, vertically beneath the black bank layer, instead of the claimed “portion of the semiconductor layer where the emission area is positioned.” In addition, Figs. 10a-c & 11a-b of the drawings show the gate electrode GA to be disposed vertically beneath the black bank layer BB. Claim Rejections – 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 3, 6, 7, 8, 9, 15, 16, 18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076). Regarding Claim 1, Kim (see, e.g., fig. 6, para.0033, para.0035) shows a display device, comprising: a substrate 111 (see, e.g., para.0085) including an emission area EA and a non-emission area DA (see, e.g., fig. 6); a thin film transistor 220 & 230 (see, e.g., para.0086) disposed on the substrate; a passivation layer 270 (see, e.g., para.0099) covering an upper portion of the thin film transistor (layers 224 & 234 of transistors 220 & 230); an overcoat layer 280 (see, e.g., para.0100) disposed on the passivation layer and having a slit or through hole CT2 (see, e.g., para.0102) recessed toward the passivation layer; a black bank layer 301 (see, e.g., para.0104) disposed on the overcoat layer and having a shape corresponding to the slit or through hole of the overcoat layer, so as to form a protrusion positioned in the slit or through hole (the protrusion is hereinafter “301P”); wherein the protrusion of black bank layer 301P overlaps with a color filter layer 320 (301P & 320 overlap in the vertical direction, see, e.g., fig. 6, para.0106). Kim, however, fails to show and a color filter layer disposed between the passivation layer and the overcoat layer, Yang (see, e.g., fig. 5, para.0079-0080), in a similar device to Kim, shows and a color filter layer CW, CR, CG, & CB disposed between the passivation layer 113 and the overcoat layer 114, Yang (see e.g., para.0050-0053) teaches the configuration of the color filter layer between the passivation and the overcoat layer, beneath the bank layer 210 & light-blocking element 200, forms a defined light emission area for each individual color portion of the color filter layer and would prevent mixing of colors and light leakage between different light emission areas. The configuration of Yang is incorporated into the device of Kim. Kim, in view of Yang, show and a color filter 320 disposed between the passivation layer 270 and the overcoat layer 280 (see , e.g., annotated figure 1). It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Yang in the device of Kim to prevent mixing of colors and light leakage between different light emission areas. PNG media_image1.png 587 1290 media_image1.png Greyscale Annotated Figure 1 Regarding Claim 2, Kim (see, e.g., para.0104), in view of Yang, shows the display device of claim 1, wherein external light incident on the emission area EA is absorbed by the protrusion of the black bank layer 301 (301 absorbs and prevents light from the emission area to enter the non-emission area, see, e.g., para.0104). Regarding Claim 3, Kim, in view of Yang, shows the display device of claim 1, wherein the black bank layer 301 is separated at the emission area, as a boundary, to form an opening (301 is separated in EA, hereinafter “301O”, see, e.g., annotated figure 1). Regarding Claim 6, Kim, in view of Yang, shows the display device of claim 3, wherein the slit or through hole of the overcoat layer CT2 is formed to have a structure surrounding the thin film transistor adjacent to the opening 301O (CT2 extends vertically and horizontally in a curved direction that surrounds the TFT, and is to the right of the opening and is therefore adjacent, see, e.g., annotated figure 1). Regarding Claim 7, Kim (see, e.g., para.0092), in view of Yang, shows the display device of claim 3, wherein the slit or through hole of the overcoat layer CT2 overlaps an upper portion of the thin film transistor 224 (an element of 220 & 230, see, e.g., para.0092) adjacent to the opening 301O (CT2 overlaps 224 of the TFT, both CT2 & TFT are adjacent to the opening by being to the right side of 301O). Regarding Claim 8, Kim, in view of Yang, shows the display device of claim 1, wherein the slit or through hole of the overcoat layer CT2 is formed in the non-emission area DA (see, e.g., fig. 6). Regarding Claim 9, Kim, in view of Yang, shows the display device of claim 1, wherein the overcoat layer 280 has a step (sidewall of 280 angled downwards from left to right, see, e.g., fig. 6) formed by the slit or through hole (the sidewall of 280 is formed by CT2), and wherein the step is formed to be inclined downwardly from the emission area EA to the non-emission area DA (from left to right as previously stated, see, e.g., fig. 6). Regarding Claim 15, Kim, in view of Yang (see, e.g., fig. 5), shows the display device of claim 1, wherein the substrate 111 includes a red subpixel R, a green subpixel G, a blue subpixel B, and a white subpixel W adjacent to each other, and wherein the slit or through hole of the overcoat layer CT2 is formed in the blue subpixel and the white subpixel (CT2 is present in all subpixels, see, e.g. annotated figure 2). Kim (see, e.g., para.0018, para.0050, para.0084) states fig. 6 is a cross-sectional view of fig. 3 which shows pixels of the display device. Yang (see, e.g. fig. 5, para.0036) shows a configuration of pixels for a display device including red, green, blue, and white subpixel as required by the claim. The pixels of Kim are replicated to show the configuration of Yang. PNG media_image2.png 833 2063 media_image2.png Greyscale Annotated Figure 2 Regarding Claim 16, Kim (see, e.g., para.0092-0093), in view of Yang, shows the display device of claim 1, wherein the thin film transistor 220 & 230 includes at least one of a driving thin film transistor 220 (see, e.g., para.0092) and a switching thin film transistor 230 (see, e.g., para.0093). Regarding Claim 18, Kim (see, e.g., para.0101-0102), in view of Yang, shows the display device of claim 1, further comprising a light emitting element 290 (see, e.g., para.0101) electrically connected to the thin film transistor, wherein the light emitting element includes: a first electrode 291 interposed between the overcoat layer 280 and the black bank layer 301, including a transparent conductive material (see, e.g., para.0102), and disposed in the emission area EA and the non-emission area DA (extends in both areas, see, e.g., fig. 6); a light emitting layer 292 (see, e.g., para.0101) disposed on the first electrode 291; and a second electrode 293 (see, e.g., para.0101) disposed on the light emitting layer. Regarding Claim 20, Kim (see, e.g., fig. 6, para.0101-0102), in view of Yang, shows the display device of claim 1, further comprising a light emitting element 290 (see, e.g., para.0101) electrically connected to the thin film transistor 220 & 230 (through CT2 & 291, see, e.g., para.0102) and including a first electrode 291 (see, e.g., para.0102), wherein a portion of the first electrode 291 is interposed between the overcoat layer 280 and the black bank layer 301 inside of the slit or through hole of the overcoat layer CT2, and contacts a side surface of the slit or through hole of the overcoat layer CT2 (291 is between the protrusion 301P and layer 280, see, e.g., fig. 6). Claims 4, 5, & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076) and further in view of Wang (US 20190157629). Regarding Claim 4, Kim, in view of Yang, shows the display device of claim 3, Kim, in view of Yang, however, fails to show wherein the slit or through hole of the overcoat layer is disposed between the opening and the thin film transistor. Wang (see, e.g., figs. 2-3, para.0032-0033), in a similar device to Kim, in view of Yang, shows a configuration wherein wherein the slit or through hole 181 of the overcoat layer 13 is disposed between the opening (area where elements 14, 15, & 17 are in direct physical contact) and the thin film transistor 12. Wang (see e.g., para.0033) states the configuration of the slit or through hole 181 between the opening and the thin film transistor would reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. The configuration of Wang is incorporated into the device of Kim, in view of Yang. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Wang in the device of Kim, in view of Yang, to reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. Regarding Claim 5, Kim, in view of Yang, shows the display device of claim 3, wherein the slit or through hole of the overcoat layer CT2 has a portion overlapping the thin film transistor 220 & 230 (the portion where CT2 overlaps elements 221 & 224 of the TFT) Kim, in view of Yang, however, fails to show wherein the slit or through hole of the overcoat layer is disposed between the opening 301O and the thin film transistor Wang (see, e.g., figs. 2-3, para.0032-0033), in a similar device to Kim, in view of Yang, shows a configuration wherein wherein the slit or through hole 181 of the overcoat layer 13 is disposed between the opening (area where elements 14, 15, & 17 are in direct physical contact) and the thin film transistor 12. Wang (see e.g., para.0033) states the configuration of the slit or through hole 181 between the opening and the thin film transistor would reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. The configuration of Wang is incorporated into the device of Kim, in view of Yang. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Wang in the device of Kim, in view of Yang, to reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. Regarding Claim 19, Kim, in view of Yang, shows the display device of claim 1, Kim, in view of Yang, however, fails to show wherein a bottom surface of the protrusion of black bank layer is disposed closer to the emission area defined by the black bank layer than a gate electrode of the thin film transistor adjacent to the protrusion of black bank layer. Wang (see, e.g., fig. 5, para.0043-0044), in a similar device to Kim, in view of Yang, shows a configuration wherein wherein a bottom surface of the light blocking structure 18 (same function as 301 of Kim) is disposed closer to the emission area defined by the light blocking structure (area where 14, 15, & 17 are in direct physical contact between elements 18) than the thin film transistor 12 adjacent to the protrusion of light blocking structure (recess 181 where 18 is located). Wang (see e.g., para.0044) states the configuration of the entire light blocking structure (including its bottom surface) closer to the emission area than the entire thin film transistor (including all its components such as the gate electrode) would reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. The configuration of Wang is incorporated into the device of Kim, in view of Yang. Kim (see, e.g., para.0087), in view of Yang and further in view of Wang, shows wherein a bottom surface of the protrusion of black bank layer 301P is disposed closer to the emission area defined by the black bank layer 301O & EA than a gate electrode 222 (see, e.g., para.0087) of the thin film transistor 220 & 230 adjacent to the protrusion of black bank layer 301P. Since the device of Wang shows the entire light blocking structure closer to the emission area than the entire film transistor, the positional limitations of the “bottom surface” & “gate electrode” are rendered obvious. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Wang in the device of Kim, in view of Yang, to reduce the harmful effects of light radiation exposure and prevent dysfunction of the thin film transistor. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076) and further in view of Liu (US 20200295099) & Nagasawa (JP 2021136287). Regarding Claim 10, Kim, in view of Yang, shows the display device of claim 1, Kim, in view of Yang, however, fails to show wherein a length of the protrusion of the black bank layer is about l µm to 10 µm. The current limitation of “length” of the protrusion is broad without a claimed direction. Any dimension relating to the size of the protrusion can anticipate the current claim, for instance width could still be can still be considered a length of the protrusion. Liu (see, e.g., fig. 5, para.0051, para.0054), in a similar device to Kim, in view of Yang, shows a configuration wherein wherein a length (in this case the width is interpreted as a length in the horizontal direction) of the protrusion of the black bank layer 7 is about l µm to 10 µm (approximately l µm to 10 µm, see, e.g., para.0045). Liu (see e.g., para.0045) states the configuration of a wider recess, forming the length dimension for the protrusion would achieve an excellent light leakage blocking and a high aperture ratio. The configuration of Liu is incorporated into the device of Kim, in view of Yang. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Liu in the device of Kim, in view of Yang, to achieve an excellent light leakage blocking and a high aperture ratio. In the case the “length” limitation is interpreted along a vertical direction, which Examiner does not concede is required, Liu (see, e.g., para.0044, para.0046) shows a configuration a deeper recess would increase the effectiveness of blocking light leakage. The depth D, length of the protrusion in the vertical direction, is a ratio relative to the thickness of the layer the planarization layer 3. A range of ratios provided is approximately 0.7:1 to approximately 1:1. The recess and the thickness of the planarization layer of Kim, in view of Yang, correspond to the slit or through-hole of the overcoat layer CT2 and the thickness of the overcoat layer 280 (color filter layer 320 was modified to be included within the pre-existing 280), respectively. Although Kim, in view of Yang does not state the thickness of the overcoat layer 280, the thickness of an overcoat/planarization layer are known in the art. Nagasawa (see, e.g., fig. 3, para.0027), in a similar device to Kim, in view of Yang and further in view of Liu, teaches the thickness of an overcoat layer 113 with a thickness of 2 µm. Nagasawa (see, e.g., para.0027) states the thickness of 2 µm would reduce stray capacitance. The thickness of Nagasawa is incorporated into the device of Kim, in view of Yang and further in view of Liu. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the thickness of Nagasawa in the device of Kim, in view of Yang and further in view of Liu, to reduce stray capacitance. Kim, in view of Yang and further in view of Liu & Nagasawa, shows wherein a length of the protrusion of the black bank layer 7 is about l µm to 10 µm 0.7:1 ratio to thickness of 2 µm produces 1.4 µm to 2 µm within the claimed range, see MPEP 2131.03(I) Anticipation of Ranges). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076) and further in view of Nakamura (US 20150171356). Regarding Claim 11, Kim, in view of Yang, shows the display device of claim 1, Kim, in view of Yang, however, fails to show wherein a distance between the protrusion of the black bank layer and the passivation layer is about 1Å to 6000 Å. Kim (see, e.g., annotated figure 1), in view of Yang, shows the distance between the protrusion of the black bank layer 301P and the passivation layer 270 is defined by the thickness of the anode 291 at the bottommost surface of the black bank layer 301. Nakamura (see, e.g., fig. 2, para.0192), in a similar device to Kim, in view of Yang, shows an anode 41 (see, e.g., para.0157, para.0192) within the slit or through hole of an overcoat layer 21 that has range of a thickness of 2000 Å to 5000 Å would be conducive to proper light emission of various colored sub-pixels in a display device. The range of thickness of the anode of Nakamura is incorporated in to the device of Kim, in view of Yang. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the range of thickness of Nakamura in the device of Kim, in view of Yang, as a range of thickness conducive for proper light emission of various colored sub-pixels in a display device. Kim, in view of Yang and further in view of Nakamura, shows wherein a distance (thickness of anode 291 is between 2000 Å and 5000 Å) between the protrusion of the black bank layer 301P and the passivation layer 270 is about 1 Å to 6000 Å. Therefore, the claimed range of a distance between the protrusion of the black bank layer and the passivation layer is held obvious over prior art that teaches an obvious range of thickness of an anode and therefore shows the distance to be 2000 Å to 5000 Å within the claimed range. See MPEP 2131.03 (I). Anticipation of Ranges. Claims 12, 13, & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076) and further in view of Liu (US 20200295099). Regarding Claim 12, Kim, in view of Yang, shows the display device of claim 1, wherein an upper surface of the color filter layer contacts a lower surface of the protrusion of black bank layer. Kim (see, e.g., para.0102) states the configuration of the anode electrode 291, currently preventing direct physical contact between the color filter layer 320 and the protrusion of the black bank layer 301P “may be formed” on 280 and “may be connected” to the drain electrode 224 of the TFT. Kim does not explicitly require this configuration. Liu (see, e.g., fig. 4), in a similar device to Kim, in view of Yang, shows an alternate configuration wherein wherein an upper surface (topmost surface where 21 contacts 22) of the color filter layer 20 (comprising 21 & 22) contacts (direct physical contact because the anode 4 is not disposed within the slit or through hole R) a lower surface of the protrusion of black bank layer 7 (bottommost surface, see, e.g., para.0045). Liu (see e.g., para.0042-0045, see, e.g., para.0049) states the alternate configuration, shown without the presence of anode 4 in the slit or through-hole R, still would provide effective light leakage blocking and a high aperture ratio. The alternate configuration of Liu is incorporated into the device of Kim, in view of Yang. As previously stated, the alternate configuration is not prevented by the specification of Kim. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the alternate configuration of Liu in the device of Kim, in view of Yang, to provide effective light leakage blocking and a high aperture ratio. Kim, in view of Yang and further in view of Liu, shows wherein an upper surface of the color filter layer 320 (although shown the limitation does not require “topmost”) contacts a lower surface (similarly, the limitation does not require “bottommost”) of the protrusion of black bank layer 301P (see, e.g., annotated figure 3). PNG media_image3.png 489 1030 media_image3.png Greyscale Annotated Figure 3 Regarding Claim 13, Kim, in view of Yang and further in view of Liu, shows the display device of claim 12, Kim, in view of Yang and further in view of Liu, in the embodiment of annotated figure 3 fails to show wherein the color filter layer includes a slit or through hole formed in an upper portion of the color filter layer, and wherein the protrusion is positioned in the slit or through hole of the color filter layer through the overcoat layer (see, e.g., annotated figure 4). The prior art of record has support to create a second embodiment that shows the missing limitations of Claim 13. Liu (see, e.g., fig. 4, para.0044) states the deeper the slit or through hole R of the overcoat layer 3 is, the more effective the light leakage blocking is. Annotated figure 1, shows the slit or through hole of the overcoat layer CT2 fully extending through the color filter layer 320 and is supported by Yang as it forms a defined light emission area for each individual color portion of the color filter layer and would prevent mixing of colors and light leakage between different light emission areas. Both configurations are supported, either the protrusion of the black bank layer 301P has direct physical contact with an upper surface of color filter layer 320 or the protrusion of the black bank layer 301P fully extends through the color filter layer 320. Thus a second embodiment of Kim, in view of Yang and further of Liu, is construed as follows and renders Claim 13 obvious. Kim, in view of Yang and further of Liu, in the second embodiment shows wherein the color filter layer 320 includes a slit or through hole (hereinafter “320O”) formed in an upper portion of the color filter layer 320 (u-shape slit of 320, see, e.g., annotated figure 4), and wherein the protrusion 301P is positioned in the slit or through hole of the color filter layer 320O through the overcoat layer (see, e.g., annotated figure 4). PNG media_image4.png 489 1030 media_image4.png Greyscale Annotated Figure 4 Regarding Claim 14, Kim, in view of Yang (see, e.g., fig. 5) and further in view of Liu, shows the display device of claim 12, wherein the substrate 111 includes a red subpixel R, a green subpixel G, a blue subpixel B, and a white subpixel W adjacent to each other (see, e.g., annotated figure 2), and wherein the color filter layer 320 is provided on the passivation layer 270 at a corresponding area of the substrate 111 where at least one of the red subpixel R, the green subpixel G, or the blue subpixel B is disposed (see, e.g., annotated figure 2). Kim (see, e.g., para.0018, para.0050, para.0084) states fig. 6 is a cross-sectional view of fig. 3 which shows pixels of the display device. Yang (see, e.g. fig. 5, para.0036) shows a configuration of pixels for a display device including red, green, blue, and white subpixel as required by the claim. The pixels of Kim are replicated to show the configuration of Yang, see annotated figure 2. The modifications of Claim 12, on which Claim 14 depends, are implied when making reference to annotated figure 2 and therefore can still be used to reject Claim 14. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180033847) in view of Yang (KR 20160054076) and further in view of Jeong (US 20120292612). Regarding Claim 17, Kim (see, e.g., para.0085-0095), in view of Yang, shows the display device of claim 1, wherein the thin film transistor 220 & 230 includes: a buffer layer 210 (see, e.g., para.0085) disposed on the substrate 111; a semiconductor layer 221 (see, e.g., para.0088) disposed on the buffer layer a gate electrode 222a-b (see, e.g., para.0090) disposed over a portion of the semiconductor layer 221 where the emission area is positioned; and a gate insulation film 240 (see, e.g., para.0095) disposed between the semiconductor layer and the gate electrode. Kim, in view of Yang, however, fails to show, the semiconductor layer including a transparent conductive material; Jeong (see, e.g., fig. 1,, para.0048), in a similar device to Kim, in view of Yang, shows a configuration wherein the semiconductor layer 215 (of thin film transistor TFT) including a transparent conductive material (transparent conductive oxide, see, e.g., para.0048); Jeong (see e.g., para.0048) states the configuration of a transparent conductive oxide as the material for a semiconductor layer of a thin film transistor would provide high performance characteristics for the thin film transistor. The configuration of Jeong is incorporated into the device of Kim, in view of Yang. It would have been obvious to at the time of filing the invention to one of ordinary skill in the art to incorporate the configuration of Jeong in the device of Kim, in view of Yang, to provide high performance characteristics for the thin film transistor. Response to Arguments Applicant's arguments filed 07/01/2026, see page 6, with regards to the rejection of claim 14 under 35 U.S.C. 112 (b) have been fully considered and are persuasive. The rejection of claim 14 under 35 U.S.C. 112 (b) has been withdrawn. With regards to the objection to the drawings of claim 17, the objection to the drawings is withdrawn. However, claim 17 is rejected under 35 U.S.C. 112 (b), see paragraphs 3-8 above. Applicant’s arguments, see pages 6-8, with respect to the prior art rejections of claim(s) 1-18 under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Dec 14, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §103, §112
Jul 01, 2026
Response Filed
Oct 01, 2026
Final Rejection mailed — §103, §112 (current)

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Patent 12622322
SEMICONDUCTOR PACKAGE HAVING ORDERED WIRE ARRANGEMENT BETWEEN DIFFERENTIAL PAIR CONNECTION PADS
3y 8m to grant Granted May 05, 2026
Patent 12610595
INTEGRATED CIRCUIT DEVICE
4y 3m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
89%
With Interview (+8.8%)
3y 4m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 20 resolved cases by this examiner. Grant probability derived from career allowance rate.

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