DETAILED ACTION
1. This action is in response to the RCE filed on 1/29/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/29/26 has been entered.
Drawings
4. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
Claims 1 and 17 recites “a gate of a second input transistor in the pair receives an output voltage” (Examiner notes: Figures 3A-3C of the current application merely shows the gate of transistor P7 receives a sampled voltage from R1, R2. The is no direction connection between the gate of transistor P7 to output voltage Vout)
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
5. Applicant’s arguments with respect to claim(s) 1 and 17 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 5, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472).
Regarding claims 1 and 17: Huang disclsoes low dropout regulator (i.e. figure 2) comprising:
an error amplifier (i.e. 220), comprising a pair of differential input transistors (i.e. M1, M2) and loads (i.e. M3, M4) respectively directly connected to the pair of differential input transistors (i.e. M1, M2), wherein, a gate of a first input transistor (i.e. M2) in the pair receives a reference voltage (i.e. Vref) and a gate of a second input transistor (i.e. M1) in the pair receives an output voltage of the low dropout regulator or a sampled voltage (i.e. from R1, R2) obtained by sampling the output voltage (i.e. Vout);
a power transistor (i.e. MP), a gate of which is coupled (i.e. electrically coupled) to an output terminal (i.e. terminal C) of the error amplifier (i.e. 220), and a drain of which serves as an output node (i.e. node B) to output the output voltage (i.e. Vout);
a second frequency compensation capacitor (i.e. Cc1), one terminal of which is directly connected to a second internal node (i.e. node at C) of the error amplifier (i.e. 220) and the other terminal of which is directly connected to the output node (i.e. node B), so as to form a left half-plane zero (i.e. function of capacitor Cc1) of the low dropout regulator (i.e. figure 2), the second internal node (i.e. node at C) is a node at which the first input transistor (i.e. M2) and the load (i.e. M4) of the first input transistor (i.e. M2) are directly connected,
but does not specifically disclose a first frequency compensation branch, comprising a first frequency compensation capacitor and a current amplifier for amplifying the current flowing through the first frequency compensation capacitor, wherein, the first frequency compensation capacitor is coupled between the output node and the current amplifier, and the current amplifier is coupled to the output terminal of the error amplifier or a first internal node of the error amplifier so as to form a first negative feedback loop in the low dropout regulator; and
Ankamreddi et al. a voltage regulator (i.e. figure 2) comprising a first frequency compensation branch (i.e. 240, 242), comprising a first frequency compensation capacitor (i.e. 242) and a current amplifier (i.e. 240) for amplifying the current flowing through the first frequency compensation capacitor (i.e. 242), wherein, the first frequency compensation capacitor (i.e. 242) is coupled between the output node (i.e. node for Vout) and the current amplifier (i.e. 240), and the current amplifier (i.e. 240) is coupled to the output terminal of the error amplifier (i.e. 210) or a first internal node of the error amplifier so as to form a first negative feedback loop (i.e. loop of 240, 242) in the low dropout regulator (i.e. 200),
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang’s invention with the regulator as disclose by Ankamreddi et al. for achieving a good transient response on the output voltage.
Regarding claim 5: Huang disclose (i.e. figure 2) zero formed by the second frequency compensation capacitor (i.e. Cc1) is fixed.
Regarding claim 16: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the first negative feedback loop comprises at least the first frequency compensation capacitor, the current amplifier and the power transistor.
Ankamreddi et al. a voltage regulator (i.e. figure 2) comprising the first negative feedback loop comprises at least the first frequency compensation capacitor (i.e. 242), the current amplifier (i.e. 240) and the power transistor (i.e. 230).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang’s invention with the regulator as disclose by Ankamreddi et al. for achieving a good transient response on the output voltage.
8. Claims 2-4 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472) and further in view of Yung et al. (US 20190146531).
Regarding claim 2: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the current amplifier comprises a first current mirror with an amplification factor greater than 1.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the current amplifier (i.e. 212) comprises a first current mirror (i.e. 910) with an amplification factor greater than 1 (i.e. ¶ 42).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 3: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the first frequency compensation capacitor is coupled to a node within a current source to which a reference branch of the first current mirror is coupled, or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the first frequency compensation capacitor (i.e. 210) is coupled (i.e. electrically coupled) to a node within a current source (i.e. 916) to which a reference branch of the first current mirror (i.e. mirror of 910) is coupled (i.e. electrically coupled), or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 4: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the current source to which the reference branch of the first current mirror is coupled includes two cascoded transistors for generating a reference current, and the first frequency compensation capacitor is coupled to a node at which the cascoded transistors are connected.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the current source (i.e. current source of 910) to which the reference branch of the first current mirror is coupled includes two cascoded transistors (i.e. 918, 922) for generating a reference current (i.e. reference current of 910), and the first frequency compensation capacitor (i.e. 210) is coupled (i.e. electrically coupled) to a node at which the cascoded transistors (i.e. 918, 922) are connected.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 18: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the current amplifier comprises a first current mirror with an amplification factor greater than 1, the first frequency compensation capacitor is coupled to a node within a current source to which a reference branch of the first current mirror is coupled, or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled, the current source to which the reference branch of the first current mirror is coupled includes two cascoded transistors for generating a reference current, and the first frequency compensation capacitor is coupled to a node at which the cascoded transistors are connected.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the current amplifier (i.e. 212) comprises a first current mirror (i.e. 910) with an amplification factor greater than 1 (i.e. ¶ 42), first frequency compensation capacitor (i.e. 210) is coupled (i.e. electrically coupled) to a node within a current source (i.e. 916) to which a reference branch of the first current mirror (i.e. mirror of 910) is coupled (i.e. electrically coupled), or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled, the current source (i.e. current source of 9910) to which the reference branch of the first current mirror is coupled includes two cascoded transistors (i.e. 918, 922) for generating a reference current (i.e. reference current of 910), and the first frequency compensation capacitor (i.e. 210) is coupled (i.e. electrically coupled) to a node at which the cascoded transistors (i.e. 918, 922) are connected.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 19: Huang disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the error amplifier includes a second current mirror used as one stage of amplifier in the error amplifier, the current amplifier is coupled to the second current mirror, so that the second current mirror further amplifies the current flowing through the first frequency compensation capacitor, and the current flowing through the second frequency compensation capacitor is amplified by at least the second current mirror, and the second frequency compensation capacitor together with at least the second current mirror forms a second negative feedback loop in the low dropout regulator.
Ankamreddi et al. disclose a voltage regulator (i.e. figure 2) comprising the current amplifier (i.e. 240) and the first frequency compensation capacitor (i.e. 242).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang’s invention with the regulator as disclose by Ankamreddi et al. for achieving a good transient response on the output voltage.
Joo et al. disclose a regulator (i.e. figures 1-2) comprising the error amplifier (i.e. 100) includes a second current mirror (i.e. mirror of 100) used as one stage of amplifier in the error amplifier (i.e. 100); and the current flowing through the second frequency compensation capacitor (i.e. Cc) is amplified by at least the second current mirror (i.e. mirror of 100), and the second frequency compensation capacitor (i.e. Cc) together with at least the second current mirror (i.e. mirror of 100) forms a second negative feedback loop (i.e. loop having capacitor Cc) in the low dropout regulator (i.e. 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Joo et al. to have the current amplifier is coupled to the second current mirror, so that the second current mirror further amplifies the current flowing through the first frequency compensation capacitor, because it adaptively adjusts a frequency of a pole of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator may operate stably in various load cases.
9. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472) and further in view of Joo et al. (US 20210397207).
Regarding claim 6: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the error amplifier includes a second current mirror used as one stage of amplifier in the error amplifier, and the current amplifier is coupled to the second current mirror, so that the second current mirror further amplifies the current flowing through the first frequency compensation capacitor.
Ankamreddi et al. a voltage regulator (i.e. figure 2) comprising the current amplifier (i.e. 240) and the first frequency compensation capacitor (i.e. 242)
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang’s invention with the regulator as disclose by Ankamreddi et al. for achieving a good transient response on the output voltage.
Joo et al. disclose a regulator (i.e. figures 1-2) comprising the error amplifier (i.e. 100) includes a second current mirror (i.e. mirror of 100) used as one stage of amplifier in the error amplifier (i.e. 100).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Joo et al. to have the current amplifier is coupled to the second current mirror, so that the second current mirror further amplifies the current flowing through the first frequency compensation capacitor, because it adaptively adjusts a frequency of a pole of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator may operate stably in various load cases.
Regarding claim 7: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the current flowing through the second frequency compensation capacitor is amplified by at least the second current mirror, and the second frequency compensation capacitor together with at least the second current mirror forms a second negative feedback loop in the low dropout regulator.
Joo et al. disclose a regulator (i.e. figures 1-2) comprising the current flowing through the second frequency compensation capacitor (i.e. Cc) is amplified by at least the second current mirror (i.e. mirror of 100), and the second frequency compensation capacitor (i.e. Cc) together with at least the second current mirror (i.e. mirror of 100) forms a second negative feedback loop (i.e. loop having capacitor Cc) in the low dropout regulator (i.e. 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Joo et al., because it adaptively adjusts a frequency of a pole of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator may operate stably in various load cases.
10. Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472) and further in view of Stanescu et al. (US 20030102851).
Regarding claim 10: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the load directly connected to the first input transistor comprises a third current mirror complementary to the type of the first input transistor, and the load directly connected to the second input transistor comprises a fourth current mirror complementary to the type of the second input transistor, and the error amplifier further includes a second current mirror, wherein, the reference branch of the second current mirror is coupled to the output branch of the third current mirror, the output branch of the second current mirror and the output branch of the fourth current mirror are coupled at a node which is the output terminal of the error amplifier.
Stanescu et al. disclose a regulator (i.e. figures 1) comprising the load (i.e. load of 102) directly connected to the first input transistor (i.e. 201) comprises a third current mirror (i.e. 205, 203) complementary to the type of the first input transistor (i.e. 201), and the load (i.e. load of 102) directly connected to the second input transistor (i.e. 202) comprises a fourth current mirror (i.e. 204, 206) complementary to the type of the second input transistor (i.e. 202), and the error amplifier (i.e. 102) further includes a second current mirror (i.e. 209, 210), wherein, the reference branch of the second current mirror (i.e. 209, 210) is coupled (i.e. electrically coupled) to the output branch of the third current mirror (i.e. 205, 206), the output branch of the second current mirror (i.e. 209, 210) and the output branch of the fourth current mirror (i.e. 204, 206) are coupled at a node which is the output terminal of the error amplifier (i.e. 102).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Stanescu et al., in order for the inconvenience and time-consuming of changing the hardware can be improved.
Regarding claim 20: Huang disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the load directly connected to the first input transistor comprises a third current mirror complementary to the type of the first input transistor, and the load directly connected to the second input transistor comprises a fourth current mirror complementary to the type of the second input transistor, and the error amplifier further includes a second current mirror, wherein, the reference branch of the second current mirror is coupled to the output branch of the third current mirror, the output branch of the second current mirror and the output branch of the fourth current mirror are coupled at a node which is the output terminal of the error amplifier.
Stanescu et al. disclose a regulator (i.e. figures 1) comprising the error amplifier (i.e. 102) includes a pair of differential input transistors (i.e. 207, 208) and loads (i.e. load of 102) respectively directly connected to the pair of differential input transistors (i.e. 207, 208), wherein, a gate of a first input transistor (i.e. 207) in the pair receives the reference voltage (i.e. Vref) and a gate of a second input transistor (i.e. 208) in the pair receives the output voltage or the sampled voltage (i.e. from Vout), wherein, the second internal is a node (i.e. node of 102) at which the first input transistor (i.e. 207) and a load (i.e. load of 102) of the first input transistor (i.e. 207) are directly connected, the load directly connected to the first input transistor (i.e. 207) comprises a third current mirror (i.e. 205, 203) complementary to the type of the first input transistor (i.e. 207), and the load directly connected to the second input transistor (i.e. 202) comprises a fourth current mirror (i.e. 204, 206) complementary to the type of the second input transistor (i.e. 202), and the error amplifier further includes a second current mirror (i.e. 209, 210), wherein, the reference branch of the second current mirror (i.e. 209, 210) is coupled (i.e. electrically coupled) to the output branch of the third current mirror (i.e. 205, 203), the output branch of the second current mirror (i.e. 209, 210) and the output branch of the fourth current mirror (i.e. 204, 206) are coupled at a node which is the output terminal of the error amplifier (i.e. 102).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Stanescu et al., in order for the inconvenience and time-consuming of changing the hardware can be improved.
11. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472) and Stanescu et al. (US 20030102851) and further in view of Yung et al. (US 20190146531).
Regarding claim 11: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the current amplifier comprises a first current mirror with an amplification factor greater than 1, the first frequency compensation capacitor is coupled to a node within a current source to which the reference branch of the first current mirror is coupled, or is coupled to a node at which the reference branch of the first current mirror and the current source are coupled, a drain of the output transistor of the first current mirror is coupled to a drain of the reference transistor of the second current mirror, so that the first frequency compensation capacitor, together with at least the first current mirror, the second current mirror, and the power transistor, forms the first negative feedback loop.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the current amplifier (i.e. 212) comprises a first current mirror (i.e. 910) with an amplification factor greater than 1 (i.e. ¶ 42), the first frequency compensation capacitor (i.e. 210) is coupled (i.e. electrically coupled) to a node within the current source (i.e. 916) to which a reference branch of the first current mirror (i.e. mirror of 910) is coupled (i.e. electrically coupled), or is coupled to a node at which the reference branch of the first current mirror and its current source are coupled, a drain of the output transistor of the first current mirror (i.e. 910) is coupled (i.e. electrically coupled) to a drain of the reference transistor of the second current mirror (i.e. 131, 133), so that the first frequency compensation capacitor (i.e. 210), together with at least the first current mirror (i.e. 910), the second current mirror (i.e. 131, 133), and the power transistor (i.e. 202), forms the first negative feedback loop (i.e. loop of 202, 210, current mirrors of 212).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 12: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the first input transistor and the second input transistor are PMOS transistors, the third current mirror and the fourth current mirror are NMOS current mirrors, the second current mirror and the first current mirror are PMOS current mirrors, the current source to which the reference branch of the first current mirror is coupled includes two cascoded NMOS transistors for generating a reference current, and the first frequency compensation capacitor is coupled to a node at which the cascoded NMOS transistors are connected.
Joo et al. disclose a regulator (i.e. figures 1-2) comprising the first input transistor and the second input transistor are NMOS transistors, the third current mirror and the fourth current mirror are PMOS current mirrors, the second current mirror is NMOS current mirror. However, it would have been an obvious matter of design choice to modify Joo et al.’s invention to have the first input transistor and the second input transistor are PMOS transistors, the third current mirror and the fourth current mirror are NMOS current mirrors, the second current mirror is PMOS current mirror to increase the regulator efficiency, since applicant has not discloses that PMOS transistors solve any stated problem or is for any particular purpose and it appears that the invention would perform equally well with Joo et al.’s invention.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Joo et al., because it adaptively adjusts a frequency of a pole of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator may operate stably in various load cases.
Yung et al. disclose a voltage regulator (i.e. figure 3 and 9B) comprising the current amplifier (i.e. 212) comprises a first current mirror (i.e. 910) is PMOS current mirror, the current source (i.e. 916) to which the reference branch of the first current mirror (i.e. 910) is coupled includes two cascoded NMOS transistors (i.e. 918, 922) for generating a reference current (i.e. current of 924), and the first frequency compensation capacitor (i.e. 210) is coupled to a node at which the cascoded NMOS transistors (i.e. 4918, 922) are connected.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Yung et al., because it would be beneficial to enhance the transient response of the regulator to compensate for such a voltage dip to maintain regulation.
Regarding claim 13: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the third current mirror and the second current mirror both have a current amplification factor greater than 1, and the current flowing through the second frequency compensation capacitor is amplified by at least the third current mirror, the second current mirror and the power transistor, so that the second frequency compensation capacitor, together with at least the third current mirror, the second current mirror and the power transistor, forms a second negative feedback loop in the low dropout regulator.
Joo et al. disclose a regulator (i.e. figures 1-2) comprising the third current mirror (i.e. 121, 123) and the second current mirror (i.e. 131, 133), and the current flowing through the second frequency compensation capacitor (i.e. Cc) is amplified by at least the third current mirror (i.e. 121, 123), the second current mirror (i.e. 131, 133) and the power transistor (i.e. 310), so that the second frequency compensation capacitor (i.e. Cc), together with at least the third current mirror (i.e. 121, 123), the second current mirror (i.e. 131, 133) and the power transistor (i.e. 310), forms a second negative feedback loop (i.e. loop of 100 having the current mirrors, Cc, 311) in the low dropout regulator (i.e. 10).
Furthermore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Huang and Joo et al.’s invention to have the third current mirror and the second current mirror both have a current amplification factor greater than 1 to increase the regulator efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang and Ankamreddi et al.’s invention with the regulator as disclose by Joo et al., because it adaptively adjusts a frequency of a pole of the output of the error amplifier based on the control voltage. Therefore, the LDO regulator may operate stably in various load cases.
12. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10768650) in view of Ankamreddi et al. (US 11630472) and further in view of El-Nozahi et al. (US 20140266106).
Regarding claim 14: Huang discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the output node is capable of being coupled to an off-chip load capacitor, the off-chip load capacitor is located outside the chip where the low dropout regulator is located, and the capacitance value of the off-chip load capacitor is of a magnitude level of μF, and the capacitance values of the first and second frequency compensation capacitors are of a magnitude level of pF.
EL-Nozahi et al. disclose a regulator (i.e. figure 2) comprising the output node is capable of being coupled to an off-chip load capacitor (i.e. CL), the off-chip load capacitor (i.e. CL) is located outside the chip where the low dropout regulator (i.e. 200) is located, and the capacitance value of the off-chip load capacitor (i.e. CL) is of a magnitude level of μF (i.e. ¶ 25).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Huang’s invention with the regulator as disclose by EL-Nozahi et al. to achieve better performance parameters.
Furthermore, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Huang and EL-Nozahi et al.’s invention to have the capacitance values of the first and second frequency compensation capacitors are of a magnitude level of pF to increase the regulator efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 15: Huang discloses the claimed invention except for the equivalent capacitance of the output terminal of the error amplifier is of a magnitude level of pF. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to modify Huang’s to have the equivalent capacitance of the output terminal of the error amplifier is of a magnitude level of pF to increase the regulator efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/ Primary Examiner, Art Unit 2838