DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-9 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable World Intellectual Property Organization International Publication Number WO 2020/257044 A1 (Schaeffer) in view of US Patent Application Publication No. US 2022/0392516 A1 (Cha) in further view of US Patent Application Publication No. US 2007/0294588 Al (Coulson).
Regarding claim 1 and analogous claims 9 and 17:
Schaeffer discloses, a memory device (110) comprising: a memory array (170) comprising a plurality of segments (rows of memory cells (205), arranged on wordlines and sensed into sense component, which may then be corrected with ECC. The sets of memory cells arranged on a wordline may be read together, such as 128 or 256 bits of data [0051-0067] [0086] [Fig. 2]); and control logic, operatively coupled with the memory array, to perform operations comprising: receiving, from a memory sub-system controller associated with the memory device, a request to perform a memory access operation on a segment of the plurality of segments of the memory array; performing the memory access operation on the segment of the memory array (by disclosing that the local memory controller (260) (which includes logic [0033]) including the row decoder (220), column decoder (225), sense component (245), and ECC block (265) as part of the local memory controller (160) of a memory die (160) including the memory array (170) may be arranged to perform a read operation in response to a read request received over the memory channels (115) [0040] [0051-0067] [Figs. 1-2]) determining a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses and providing the health status for the segment to the memory sub-system controller in response to receiving the request to perform the memory access operation, wherein the plurality of possible health statuses comprises a pass status indicating that the value of the health metric meets an expected value, a fail status indicating that the value of the health metric exceeds a maximum allowable value, and an intermediate status (by disclosing that the local memory controller may output the read data to the external memory controller, and along with the read data, includes an indicator of the state of error, which may include three or more possible states of error [0050]. The three states of error may include (1) no error (a pass status indicating that the value of the health metric meets an expected value), (2) a corrected error (an intermediate status) or (3) an uncorrected error (a fail status indicating that the value of the health metric exceeds a maximum allowable value) [0075]).
Schaeffer does not explicitly disclose, but Cha teaches, wherein determining the health status for the segment comprises determining a value of a health metric of the segment and comparing the value of the health metric to a set of thresholds associated with the plurality of possible health statuses (by teaching that a health status may be determined for a memory segment, which may include comparing a number of error bits to a second reference value and a first reference value (lower and higher threshold, respectively) wherein the pass status indicates that the segment can continue to be used, and wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is determined based on which of the plurality of possible health statuses is determined for the segment, such that a different action is performed for each of the plurality of possible health statuses (by teaching that the controller can continue normal operation (the segment can continue to be used) when the number of error bits is below both thresholds (i.e. pass status indicating that the value of the health metric meets an expected value) because the health status check operation ends (RINC end) (Patrol Read End), that the controller may perform a reclaim operation on the memory when the number of error bits are above the highest threshold (i.e., fail status indicating that the value of the health metric exceeds a maximum allowable value (i.e., the higher threshold)) (S112) (S212), and that the controller may perform a patrol read on the memory by registering the target wordline in a health buffer when the number of error bits is not above the highest threshold, but is above the lower threshold (at least one intermediate status) (S114) (S214). The system therefore performs three different actions for each of the three different conditions (such that a different action is performed for each of the plurality of health statuses) [Figs. 7-8] [0086-0089] [0093-0094] [0096]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified determining and communicating the different error statuses for a segment of memory read by a read operation as taught by Schaeffer to include determining the error status according to the number of error bits compared to two thresholds, so that the controller can either perform a reclaim, a patrol read, or resume normal operation based on the condition of the wordline as referenced to the two thresholds based on a number of error bits as taught by Cha.
One of ordinary skill in the art would have been motivated to make this modification because sharing the health information for different wordlines and performing corresponding operations based on the health information provides an improvement in the reliability of data as taught by Cha in [0004] [0050] [0104] [0151].
Cha does not explicitly disclose, but Coulson teaches, and wherein the fail status indicates that the segment should be retired and no longer used; (by teaching that if an uncorrectable number of errors is encountered in read data from a block, or if the number of errors is above a second higher error threshold, the block can be assigned to a bad state, where it is no longer used to store data [0012] [0017] [0027] [0029]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the error thresholds used to determine actions to be performed on a segment of data as taught by Schaeffer in view of Cha to include retiring a block and not using it to store data if it is found with a high enough error threshold.
One of ordinary skill in the art would have been motivated to make this modification because marking a block as bad can reduce the danger of integrity of data stored in blocks of memory that would other extend error correction beyond its capabilities as taught by Coulson in [0009] [0012].
Regarding claim 6 and analogous claims 14 and 18:
The memory device of claim 1 is made obvious by Schaeffer in view of Cha in further view of Coulson (Schaeffer-Cha-Coulson).
Schaeffer further discloses, wherein the at least one intermediate status comprises at least one of an intermediate pass status or an intermediate fail status, wherein the intermediate pass status indicates the segment passed health checks but may be trending towards failure, and wherein the intermediate fail status indicates the segment failed but may be recoverable (by teaching the health status indicating that there was an error, but it was corrected (i.e., the segment passed health checks). Furthermore, reading a memory cell degrades it, or reading nearby memory cells may disturb it (but may be trending toward failure) [0067]).
Regarding claim 7 and analogous claims 15 and 19:
The memory device of claim 6 is made obvious by Schaeffer-Cha-Coulson.
Schaeffer does not explicitly disclose, but Cha teaches, wherein responsive to providing the intermediate pass status for the segment to the memory sub-system controller, the memory sub-system controller is to schedule a health scan to be performed on the segment of the memory array (by teaching that responsive to determining that the number of error bits are between the two thresholds, such that the health status is an intermediate status (marginal pass), the target wordline may be added to a health buffer so that a patrol read may be performed on the wordline at a later time (schedule a health scan to be performed on the segment of the memory array) [0082] [0087-0088]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified determining and communicating the different error statuses for a segment of memory read by a read operation as taught by Schaeffer to include determining the error status according to the number of error bits compared to two thresholds, so that the controller can either perform a reclaim, a patrol read, or resume normal operation based on the condition of the wordline as referenced to the two thresholds based on a number of error bits as taught by Cha.
One of ordinary skill in the art would have been motivated to make this modification because sharing the health information for different wordlines and performing corresponding operations based on the health information provides an improvement in the reliability of data as taught by Cha in [0004] [0050] [0104] [0151].
Regarding claim 8 and analogous claim 16 and 20:
The memory device of claim 6 is made obvious by Schaeffer-Cha-Coulson.
Schaeffer does not explicitly disclose, but Cha teaches, wherein responsive to providing an intermediate fail status for the segment to the memory sub-system controller, the memory sub-system controller is to perform a data recovery operation to salvage the segment of the memory array (by teaching that responsive to determining that the number of error bits are between the two thresholds, such that the health status is an intermediate status (intermediate fail), the target wordline may be added to a health buffer so that a patrol read may be performed on the wordline at a later time. When the patrol read is performed at the later time, if the number of error bits has grown above the first error threshold, then the memory is reclaimed (perform a data recovery operation to salvage the segment of the memory array) [0082] [0087-0088] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified determining and communicating the condition of the memory array, based on a number of error bits, as compared to two thresholds as taught by Boehm to include determining the number of error bits for a specific wordline in response to a request to perform a read, patrol read, or other background operation on the wordline, determining the condition for the wordline according to comparison of the number of error bits to two reference values, and communicating the condition of the wordline to the controller, so that the controller can either perform a reclaim, a patrol read followed by a read reclaim (when the health information indicates the number of error bits is between the two thresholds (intermediate status, marginal pass) and then is retested and the error bits are above the first threshold), or resume normal operation based on the condition of the wordline as referenced to the two thresholds based on error bits as taught by Cha.
One of ordinary skill in the art would have been motivated to make this modification because sharing the health information for different wordlines in different health monitoring operations provides an improvement in the reliability of data as taught by Cha in [0004] [0050] [0151].
Allowable Subject Matter
Claims 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4 and analogous claim 12:
The closest prior art of record does not teach “wherein the plurality of possible health statuses comprise a pass status indicating that the value of the health metric meets an excepted value, a fail status indicating that the value of the health metric exceeds a maximum allowable value, and at least one intermediate status, wherein the pass status indicates that the segment can continue to be used, and wherein the fail status indicates that the segment should be retired and no longer used” because US Patent Application Publication No. US 2020/0411131 A1 (Linnen) does not teach retiring a block and that it can be no longer used after a charge pump clock monitor reaches a second threshold, and the claims require the health metric to include at least one of a charge pump clock monitor (CPCM) metric, a lagging plane pulse count (LPC) metric, an erase CPCM metric, or a wordline short sensor metric. Furthermore, US Patent Application Publication No. US 20210173734 A1 (Lee) – teaches that a word line short is a critical failure that results in a block being marked as bad. There is no intermediate classification for a word line failure [0078], and US Patent Application Publication No. US 20180053559 A1 (Kaneko) – teaches that a word line leakage determination is a binary classification that results in a “pass” or “fail” classification and not a third, intermediate, classification. Accordingly, one of ordinary skill in the art would not have been motivated to modify the prior art to arrive at the claimed invention as the prior art does not teach such pass, intermediate, and fail statuses for metrics including CPCM metrics, LPC metrics, or WLSS metrics.
Response to Arguments/Amendments
In response to the amendments to the claims, a new 35 USC §103 rejection has been made over Schaeffer-Cha-Coulson. As applicant’s arguments do not address this new combination, Applicant’s arguments are moot.
The Examiner apologizes for misreading the claim dependency and incorrectly concluding that claim 5 depended on the subject matter in claim 4. Accordingly, this action is designated as non-final.
Conclusion
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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