DETAILED ACTION
Claims 1 – 33 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/25/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 12-17 and 23-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goudie et al (US 2022/0114016, hereinafter referred to as Goudie).
As per claims 1, 12 and 23:
Taking claim 1 as exemplary: Goudie discloses apparatus comprising :circuitry configured to: assign first memory storage space of a first memory for a first vector memory access instruction, responsive to the first vector memory access instruction (Goudie: paragraph [0015] data store and linked-list RAM); store requested data of the first vector memory access instruction in the first memory storage space, responsive to the requested data returning from a memory subsystem (Goudie: paragraph [0015], the task builder takes the data and adds it to the linked list based on the respective item ID until the last data item); and send a notification to an execution circuit processing a wavefront indicating that the requested data is ready for access (Goudie: paragraph [0015] Task builder indicates when the task is ready for scheduling, the task scheduler working for the parallel processing subsystem receives the indication and schedules the task for processing by the parallel processing subsystem; paragraph [0044] interpreting the parallel processing subsystem as equivalent to the claimed execution circuit processing a wavefront, as the parallel processing subsystem performs concurrent processing on multiple threads and applicant’s specification describes a wavefront as a multiple threads grouped and operating on multiple data items concurrently). As per claims 2, 13 and 24:
Taking claim 2 as exemplary: Goudie discloses the circuitry is further configured to store the requested data of the first vector memory access instruction in the first memory storage space in place of a vector register of a vector register file (Goudie: paragraph [0015], data store).
As per claims 3, 14 and 25:
Taking claim 3 as exemplary: Goudie discloses the circuitry is further configured to send the requested data to the execution circuit, responsive to receiving an indication from the execution circuit specifying that the execution circuit is ready for the requested data (Goudie: paragraph [0015] the scheduler sends the data to the parallel processing subsystem when ready).
As per claims 4, 15 and 26:
Taking claim 4 as exemplary: Goudie discloses the circuitry is further configured to maintain the requested data in the first memory storage space until receiving an indication from the execution circuit specifying that the execution circuit is ready for the requested data (Goudie: paragraph [0015] the task builder keeps the data until the task scheduler can send the data to the parallel processing subsystem, the moving of data to the parallel processing subsystem is an indication that it is ready for the data).
As per claims 5, 16 and 27:
Taking claim 5 as exemplary: Goudie discloses the circuitry is further configured to assign the first memory storage space based on an offset value indicated by the first vector memory access instruction (Goudie: paragraph [0015], interpreting the offset value to be equivalent to the data items being mapped to a respected item ID).
As per claims 6, 17 and 28:
Taking claim 6 as exemplary: Goudie discloses the circuitry is further configured to assign the first memory storage space based on a base address stored in a configuration register (Goudie: paragraph [0015], interpreting the linked list RAM as performing the functionality of a based address stored in a configuration register).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-12, 21-22 and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Goudie as applied to claims 1, 12 and 23 above, and further in view of Li et al (US 2007/0229521, hereinafter referred to as Li).
As per claims 10, 21 and 32:
Taking claim 10 as exemplary: Goudie does not specifically disclose the circuitry is further configured to assign second memory storage space of a second memory at a different level of the memory subsystem than the first memory, responsive to an indication specifying that the first memory is full.
However, Li teaches the circuitry is further configured to assign second memory storage space of a second memory at a different level of the memory subsystem than the first memory, responsive to an indication specifying that the first memory is full (Li: paragraph [0044], move data to a different memory level if the current level becomes full), in order to ensure that the data is stored rather than replaced by new data (Li: Paragraph [0044]).
It would have been obvious to one of ordinary skill in the art at the time of filing for Goudie to implement assigning second memory storage space of a second memory at a different level of the memory subsystem than the first memory, responsive to an indication specifying that the first memory is full as taught by Li in order to ensure that the data is stored rather than replaced by new data (Li: Paragraph [0044]).
As per claims 11, 22 and 33:
Taking claim 11 as exemplary: Goudie does not specifically disclose the circuitry is further configured to assign buffer storage space of a buffer different from any memory of the memory subsystem, responsive to an indication specifying that the first memory is full.
However, Li teaches the circuitry is further configured to assign buffer storage space of a buffer different from any memory of the memory subsystem, responsive to an indication specifying that the first memory is full (Li: paragraph [0044], move data to a different memory if the current level becomes full), in order to ensure that the data is stored rather than replaced by new data (Li: Paragraph [0044]).
It would have been obvious to one of ordinary skill in the art at the time of filing for Goudie to implement assigning buffer storage space of a buffer different from any memory of the memory subsystem, responsive to an indication specifying that the first memory is full as taught by Li in order to ensure that the data is stored rather than replaced by new data (Li: Paragraph [0044]).
Allowable Subject Matter
Claims 7-9, 18-20 and 29-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, either alone or in combination, fail to teach the claim limitations of the circuitry is further configured to store the requested data in a first partition of a plurality of partitions of the first memory, responsive to the first vector memory access instruction corresponds to a collective operation; when taken in combination with the limitation set forth in each of the independent claims. The use of a plurality of cache partitions allows for different types of operations to be stored in different partitions within the cache.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rusakovich (US 2023/0350786) teaches the use of data ready indicators in memory to alert the processor that operations are ready. Koh et al (US 12,306,777) teaches the use of collective compute operations. Fok et al (US 2023/0133088) teaches the processor will receive a notification once data is ready for reading.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY K HUSON whose telephone number is (571)270-3430. The examiner can normally be reached Monday - Friday 7:00 - 3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZACHARY K HUSON/Primary Examiner, Art Unit 2181