DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings were received on 7/16/2026. These drawings are acceptable. The objection regarding the drawings has been withdrawn.
Specification
The objection to the specification has been withdrawn in light of Applicant’s amendments.
Claim Objections
The objection to claim 20 has been withdrawn in light of Applicant’s amendments.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 1, 3, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fornara (US 20200227517 A1) in view of Kar et al. (US 20220415880 A1, hereinafter referred to as "Kar"), Chiu et al. (US 20230008614 A1, hereinafter referred to as "Chiu"), Smith et al. (US 20190172828 A1, hereinafter referred to as "Smith"), and Huang et al.(US 20170084603 A1, hereinafter referred to as "Huang").
In regards to claim 1, Fornara teaches a passive device including: a first semiconductor region (N+ in Fornara figure 1); a second semiconductor region (P+ in Fornara figure 1); and a third semiconductor region laterally extending between and directly contacting facing sidewalls of the first and second semiconductor regions along an entire height of each of the facing sidewalls (INT in Fornara figure 1); wherein the first semiconductor region, the second semiconductor region and the third semiconductor region are in a second direction (they are aligned in a line in a direction); a frontside contact in contact with the first semiconductor region (C in Fornara figure 1);
Fornara does not teach a first backside contact in contact with the second semiconductor region.
Kar teaches a passive device with a first backside contact in contact with the second semiconductor region (122A in Kar figure 1A). Kar also teaches that this allows for direct connection to the backside with potential resistance benefit (Kar paragraph 0023).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the backside contact of Kar in order to directly connect the passive device to the backside with potential resistance benefits.
Fornara does not teach a backside interlevel dielectric embedding the first backside contact, nor a transistor including: a first and a second source/drain region; and a gate separating the first and the second source/drain regions; wherein the first and second source/drain regions and the gate are in a first direction; a second backside contact below the second source/drain region;
Chiu teaches a structure comprising: a transistor (102A in Chiu figure 26A) including: a first and a second source/drain region (110N2 and 110N3 in Chiu figure 26A); and a gate separating the first and the second source/drain regions (112N2 in Chiu figure 26A); wherein the first and second source/drain regions and the gate are in a first direction (they are aligned in a line in a direction); a second backside contact below the second source/drain region (154 in Chiu figure 26A); Chiu further teaches a backside interlevel dielectric embedding the first backside contact (142A in Chiu figure 26A).
Kar teaches that in back-end-of-line (BEOL) semiconductor structures, “the individual devices … are interconnected with wiring on the wafer” and furthermore that it “includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections” (Kar paragraph 0020). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add in the interlevel dielectric of Chiu in order to facilitate the chip-to-package connections in a back-end-of-line structure. Furthermore, the transistor and the passive device are completely disclosed by the aforementioned 2 references, except neither reference combines both of them together. A transistor is a common component in nearly all electronics, and a diode-like passive device is often added into these for uses such as ESD protection (Kar paragraph 0023). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the transistor of Chiu with the passive device of Kar.
Fornara, Chiu, and Kar do not teach a pair of diffusion breaks located on either side of the passive device; nor that the first direction is orthogonal to the second.
Smith teaches any suitable number of diffusion breaks (20 in Smith figure 4) to separate adjacent standard cells of a FET device (paragraph 0059). Smith also teaches that these prevent diffusion between the cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the diffusion breaks of Smith to the combined device of Fornara, Chiu, and Kar in order to prevent diffusion between adjacent devices and separate adjacent devices.
Huang teaches that the first direction is orthogonal to the second (in Huang figure 16, source fins 822, gate 810 and drain fins 824 form a first direction, D1, and the diodes, which are formed by n-drain fins, the p-substrate, and the p-typed second doped fin, are in a second direction, D2. D1 and D2 are orthogonal to each other [paragraph 0066]). Huang teaches that this modified embodiment changes the direction in which current flows while maintaining being formed for bypassing the ESD currents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the combined devices of Fornara, Chiu, Kar, and Smith orthogonally to allow for a different current flow.
Furthermore, it has been found in previous court decisions that a simple rearrangement of parts that does not modify the operation of the device do not constitute a patentable limitation (See MPEP 2144.04 VI C, and In re Japikse, 181 F.2d 1019, 86 USPQ 70). In this case, the relative orientation of the elements as claimed has not been shown to change the operation of these separate devices, and thus it would be an obvious matter of rearranging the parts for any particular application.
In regards to claim 3, Fornara in view of Kar, Chiu, Smith, and Huang teach all of the limitations of claim 1. Fornara further discloses that the first semiconductor region and the second semiconductor region are oppositely doped (the first semiconductor region N+ is N+ doped and the second semiconductor region P+ is P+ doped, see Fornara paragraph 0061).
In regards to claim 5, Fornara in view of Kar, Chiu, Smith, and Huang teach all of the limitations of claim 1. Fornara further teaches that the third semiconductor region has a dopant concentration of 0 to 5x1018cm-3. (Fornara paragraph 0061, INT is intrinsic, or undoped, corresponding to a doping concentration of 0).
In regards to claim 6, Fornara in view of Kar, Chiu, Smith, and Huang teach all of the limitations of claim 1. Fornara further teaches that the first semiconductor region has a dopant concentration at least two times that of the third semiconductor region (Fornara paragraph 0061, Since the first semiconductor region is N+ doped and has a nonzero doped concentration, and the third semiconductor region INT is undoped, N+ must have a higher concentration than twice the INT region’s concentration of 0).
In regards to claim 7, Fornara in view of Kar, Chiu, Smith, and Huang teach all of the limitations of claim 1. Furthermore, the combined invention shows the passive device is above the backside interlevel dielectric (the backside contact 122A of Kar is fully below the rest of the passive device, and thus if embedded with interlevel dielectric as in Chiu, the passive device would be fully above the interlevel dielectric).
In regards to claim 8, Fornara in view of Kar, Chiu, Smith, and Huang teach all of the limitations of claim 1. Chiu further discloses a first placeholder material under the first source/drain (the area above 110B in Chiu figure 26A on the backside of the device is a material that can be removed and replaced with another material, and is thus can be a placeholder material).
Fornara further discloses a second placeholder material under the first semiconductor region (ONO in Fornara figure 1 is a material that can be removed and replaced with another material, and is thus can be a placeholder material).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar, Chiu, Smith, and Huang as applied to claim 1 above, and further in view of Xie et al. (US 20210217654 A1, hereinafter referred to as "Xie").
In regards to claim 2, Fornara in view of Kar, Chiu, Smith and Huang teach all of the limitations of claim 1. Fornara does not explicitly disclose a protective liner in contact with the first and second semiconductor regions; and a middle of line dielectric over the protective liner and in contact with the third semiconductor region.
Xie teaches a protective liner in contact with the first and second semiconductor regions (702 in Xie figure 7A); and a middle of line dielectric over the conformal protective liner (704 in Xie figure 7A) and in contact with the third semiconductor region (as disposed in Xie, the dielectric would be over the liner over the semiconductor bridge, thus in contact with it).
Xie teaches that the “interlayer dielectric 704 is formed over the liner 702” and that “the interlayer dielectric 704 serves as an isolation structure for the semiconductor device” (Xie paragraph 0068).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Fornara in view of Kar, Chiu, Smith, and Huang with the liner and interlayer dielectric of Xie in order to electrically isolate the device.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar, Chiu, Smith, and Huang as applied to claim 1 above, and further in view of Jentzsch et al. (US 20240136800 A1, hereinafter referred to as "Jentzsch").
In regards to claim 4, Fornara in view of Kar, Chiu, Smith and Huang teach all of the limitations of claim 1.
Fornara does not explicitly teach the doping concentration of the first semiconductor region in numerical units.
Jentzsch teaches the first semiconductor region has a dopant concentration from 1x1019cm-3 to 9x1021cm-3 (Jentzsch paragraph 0039).
It would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the concentration of the dopant, because it has been shown that generally differences in concentration will not support the patentability of subject matter, unless it has been shown that such concentration is critical (see MPEP 2144.05 II A). It is known in the art that higher doping concentration in a diode can, for example, narrow the depletion region, increase the switching speed, and increase the barrier potential. Moreover, since the specified range had previously been disclosed by Jentzsch, it would have been obvious to adjust the concentration of the dopant and arrive at the disclosed range by routine optimization.
Claims 9-13, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar and Chiu.
In regards to claim 9, Fornara discloses a passive device including a first semiconductor region (N+ in Fornara figure 1), a second semiconductor region (P+ in Fornara figure 1), and a third semiconductor region laterally extending between and directly contacting facing sidewalls of the first and second semiconductor regions along an entire height of each of the facing sidewalls (INT in Fornara figure 1);
Fornara does not disclose a backside contact. Fornara also does not explicitly recite a lack of a silicon substrate below the passive device, although Fornara also does not explicitly say that the substrate is silicon, and as such, if a non-silicon substrate is used, Fornara’s device would appear to meet this limitation.
Kar teaches another backside contact to the second semiconductor region of the passive device (122A in Kar figure 1A); and wherein there is no silicon substrate below the first and the second semiconductor region of the passive device (Kar describes the diodes as “substrate-less” [see paragraphs 0017 and 0022]. Furthermore, there is no silicon substrate depicted below the device in figure 1A). Kar also teaches that this allows for direct connection to the backside with potential resistance benefit (Kar paragraph 0023).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the backside contact of Kar in order to directly connect the passive device to the backside with potential resistance benefits.
Fornara does not disclose a transistor a transistor including a first and a second source/drain and a gate on the frontside; a backside contact to the second source/drain region of the transistor wherein there is no silicon substrate below the first and the second source/drain and the gate of the transistor.
Chiu discloses a semiconductor structure comprising: a frontside (below 110B in Chiu figure 26A); a backside (above 110B in figure 26A); a transistor including a first source/drain region (110N2 in Chiu figure 26A), a second source/drain region(110N3 in Chiu figure 26A) and a gate on the frontside (112N2 in Chiu figure 26A); a backside contact to the second source/drain region of the transistor (154 in Chiu figure 26A) wherein there is no silicon substrate below the first and the second source/drain and the gate of the transistor (Chiu paragraph 0050, the substrate is replaced by the ILD layer 142A. Furthermore, no silicon substrate is depicted on the backside of figure 26A);
The transistor and the passive device are completely disclosed by the aforementioned 2 references, except neither reference combines both of them together. A transistor is a common component in nearly all electronics, and a diode-like passive device is often added into these for uses such as ESD protection (Kar paragraph 0023). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the transistor of Chiu with the passive device of Fornara.
In regards to claim 10, Fornara in view of Kar and Chiu discloses all of the limitations of claim 9. Chiu further discloses a frontside contact to the first source/drain region of the transistor (138 and 140 in Chiu figure 26A provide electrical connection from source/drain regions to the front side surface [paragraph 0033]).
Fornara further discloses another frontside contact to the first semiconductor region of the passive device (C in Fornara figure 1).
In regards to claim 11, Fornara in view of Kar and Chiu discloses all of the limitations of claim 10. Chiu further discloses a placeholder material under the first source/drain region of the transistor (the area above 110B in Chiu figure 26A on the backside of the device is a material that can be removed and replaced with another material, and is thus can be a placeholder material).
Fornara further discloses another placeholder material under the first semiconductor region of the passive device (ONO in Fornara figure 1 is a material that can be removed and replaced with another material, and is thus can be a placeholder material).
In regards to claim 12, Fornara in view of Kar and Chiu discloses all of the limitations of claim 9. Fornara further discloses that the third semiconductor region is a semiconductor bridge laterally connecting the first and second semiconductor regions of the passive device (INT in Fornara figure 1 bridges between and laterally connects N+ and P+).
In regards to claim 13, Fornara in view of Kar and Chiu discloses all of the limitations of claim 12. Fornara further discloses that the semiconductor bridge has a lower dopant concentration than the first semiconductor region of the passive device (The first semiconductor region N+ is N+ doped, and thus has a higher dopant concentration than third semiconductor region INT, which is intrinsic, or undoped, silicon; see Fornara paragraph 0061).
In regards to claim 16, Fornara in view of Kar and Chiu disclose all of the limitations of claim 12.
Fornara further discloses a shallow trench isolation located under the semiconductor bridge (STI in Fornara figure 1, which is under the bridge INT).
In regard to claim 17, Fornara in view of Kar and Chiu teach all of the limitations of claim 16. Fornara further discloses that the second semiconductor region of the passive device has a bottom surface (bottom of INT in Fornara figure 1), and wherein the shallow trench isolation has a top surface (top of STI in Fornara figure 1) located at or below the bottom surface of the second semiconductor region of the passive device (the top of STI is clearly below the bottom of INT).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar and Chiu as applied to claim 12 above, and further in view of Xie.
In regard to 14, Fornara in view of Kar and Chiu discloses all of the limitations of claim 12.
Fornara does not disclose a conformal protective liner in contact with the first and second semiconductor regions of the passive device; and a middle of line dielectric over the conformal protective liner and in contact with the semiconductor bridge.
Xie teaches a conformal protective liner in contact with the first and second semiconductor regions of the passive device (702 in Xie figure 7A); and a middle of line dielectric over the conformal protective liner (704 in Xie figure 7A) and in contact with the semiconductor bridge (as disposed in Xie, the dielectric would be over the liner over the semiconductor bridge, thus in contact with it).
Xie teaches that the “interlayer dielectric 704 is formed over the liner 702” and that “the interlayer dielectric 704 serves as an isolation structure for the semiconductor device” (Xie paragraph 0068). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kar and Chiu with the liner and interlayer dielectric of Xie in order to electrically isolate the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar and Chiu as applied to claim 12 above, and further in view of Smith.
In regards to claim 15, Fornara in view of Kar and Chiu discloses all of the limitations of claim 12. Fornara does not disclose a pair of diffusion breaks located on the frontside on either side of the passive device.
Smith teaches any suitable number of diffusion breaks (20 in Smith figure 4) to separate adjacent standard cells of a FET device (paragraph 0059). Smith also teaches that these prevent diffusion between the cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the diffusion breaks of Smith to the combined device of Kar and Chiu in order to prevent diffusion between adjacent devices and separate adjacent devices.
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Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Smith and Wong et al. (US 20220328648 A1), hereinafter referred to as “Wong”.
In regards to claim 18, Chiu discloses a method of forming a semiconductor structure comprising providing a substrate having at least two active areas (substrate 106 has at least 2 active areas 108N and 108P in Chiu figure 1A), a shallow trench isolation in the substrate and between the active areas (120 in Chiu figure 1) a placeholder material embedded in portions of the active areas of the substrate (156 in Chiu figure 11A. It is a material that can be removed and replaced with another material, and is thus can be considered a placeholder material); a first semiconductor region over the placeholder material (122 to the right of 110N2 in Chiu figure 11A is made of semiconductor, and thus is a semiconductor region); and a second semiconductor region over the placeholder material (122 to the left of 110N2 in Chiu figure 11A is made of semiconductor, and thus is a semiconductor region); epitaxially growing, on the exposed facing sidewalls, a semiconductor bridge between the first and second semiconductor regions, the semiconductor bridge directly contacting the exposed facing sidewalls along an entire height of each of the exposed facing sidewalls (110N2 in Chiu figure 11A. It is made of semiconductor material and bridges the two semiconductor regions, and directly contacts the entire height of the first and second semiconductor regions’ sidewalls. 110N2 is an epitaxial structure, and thus epitaxially grown, see Chiu paragraph 0025); forming a frontside contact to the first semiconductor region (138/140 in Chiu figure 11A. The contact connects to the first semiconductor region through the third semiconductor region 110N2); and forming a backside contact to the second semiconductor region (154 in Chiu figure 26A. The contact connects to the second semiconductor region through the region 110N3).
Chiu does not explicitly disclose forming a diffusion break. Chiu also doesn’t disclose forming and removing a conformal protective liner.
Smith teaches forming a diffusion break perpendicular to the active areas on each side of the first and second semiconductor regions and the semiconductor bridge (20 in Smith figure 4. It is shown perpendicular to the active areas of the substrate below and on the side of the main device). Smith also teaches that these are used to separate adjacent cells, and furthermore that these prevent diffusion between the cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the diffusion breaks of Smith to the method of Chiu in order to prevent diffusion between adjacent devices and separate adjacent devices.
Wong teaches forming a conformal protective liner over the first semiconductor region and the second semiconductor region (206 in Wong figure 6. See Wong paragraph 0027 “a dielectric material is deposited into both the source/drain trenches 204 and the openings 205” which is over the semiconductor regions 120); and removing the conformal protective liner from between the first and second semiconductor regions to expose facing sidewalls of the first and second semiconductor regions (See Wong paragraph 0027 “in some embodiments, no dielectric material remains on the sidewall surfaces of the semiconductor layers 120”). Wong also teaches that these processes create inner spacers (Wong paragraph 0027) while still allowing the nanosheets to contact with the source/drain. Chiu’s device has inner spacers, but is silent on any specific method on how to form them (Chiu paragraph 0057).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the known method of forming inner spacers taught by Wong to form the inner spacers of Chiu, which involves the steps of forming a conformal protective liner over the first and second semiconductor regions and removing it from between them to expose inner sidewalls.
In regards to claim 19, Chiu in view of Smith and Wong teaches all of the limitations of claim 18.
Chiu further teaches replacing the substrate with a backside interlevel dielectric layer (Chiu paragraph 0050 “fin structures 108N-108P and substrate 106 […] are replaced with back-side ILD layer”).
In regards to claim 20, Chiu in view of Smith and Wong teaches all of the limitations of claim 19.
Chiu further discloses forming a second shallow trench isolation adjacent to one of the active areas (there are at least 3 shallow trench isolations 120 depicted in Chiu figure 1A).
Furthermore, with the shallow trench isolations positioned as in Chiu, the step from Wong involving forming a protective liner would form it over both of the over the shallow trench isolations, as the shallow trench isolations would be in the substrate, and the liner would be above the substrate. In addition, the step from Wong involving removing the protective liner would remove it from over the shallow trench isolations.
In regards to the step involving forming a bottom dielectric layer on the substrate wherein a bottom of the diffusion break is co-planar with a bottom of the bottom dielectric layer, Chiu discloses forming a bottom dielectric layer on the substrate (ILD 118A in Chiu figure 1A). Moreover, both this dielectric layer and the diffusion breaks of Smith have a bottom surface that is coplanar with the top of shallow trench isolations (see Smith figure 4, bottom of 20 is coplanar with top of shallow trench isolations 12). Therefore, as applied thus far, the aforementioned steps would result in a bottom of both the dielectric layer and diffusion breaks being coplanar with the top of the shallow trench isolations, and thus coplanar with each other.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar, Chiu, and Smith.
In regard to claim 21, Fornara discloses a passive device including: a first semiconductor region (N+ in Fornara figure 1); a second semiconductor region (P+ in Fornara figure 1); and a third semiconductor region laterally extending between and directly contacting facing sidewalls of the first and second semiconductor regions along an entire height of each of the facing sidewalls (INT in Fornara figure 1); a frontside contact in contact with the first semiconductor region (C in Fornara figure 1);
Fornara does not teach a first backside contact in contact with the second semiconductor region.
Kar teaches a passive device with a first backside contact in contact with the second semiconductor region (122A in Kar figure 1A). Kar also teaches that this allows for direct connection to the backside with potential resistance benefit (Kar paragraph 0023).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the backside contact of Kar in order to directly connect the passive device to the backside with potential resistance benefits.
Fornara does not teach a transistor including: a first and a second source/drain region; and a gate separating the first and the second source/drain regions; a second backside contact below the second source/drain region. Fornara also does not teach a backside interlevel dielectric embedding the first backside contact.
Chiu discloses a semiconductor structure comprising: a transistor including: a first and a second source/drain region (110N2 and 110N3 in Chiu figure 26A); and a gate separating the first and the second source/drain regions (112N2 in Chiu figure 26A); a second backside contact below the second source/drain region (154 in Chiu figure 26A); Chiu further teaches a backside interlevel dielectric embedding the first backside contact (142A in Chiu figure 26A).
Kar teaches that in back-end-of-line (BEOL) semiconductor structures, “the individual devices … are interconnected with wiring on the wafer” and furthermore that it “includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections” (Kar paragraph 0020). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add in the interlevel dielectric of Chiu to the device of Fornara in order to facilitate the chip-to-package connections in a back-end-of-line structure. Furthermore, the transistor and the passive device are completely disclosed by the aforementioned references, except neither reference combines both of them together. A transistor is a common component in nearly all electronics, and a diode-like passive device is often added into these for uses such as ESD protection (Kar paragraph 0023). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the transistor of Chiu with the passive device of Fornara.
Fornara does not teach a pair of diffusion breaks located on either side of the passive device.
Smith teaches any suitable number of diffusion breaks (20 in Smith figure 4) to separate adjacent standard cells of a FET device (paragraph 0059). Smith also teaches that these prevent diffusion between the cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the diffusion breaks of Smith to the combined device of Fornara and Chiu in order to prevent diffusion between adjacent devices and separate adjacent devices.
In regard to claim 22, Fornara in view of Kar, Chiu, and Smith teach all of the limitations of claim 21. Fornara further teaches that the third semiconductor region has a dopant concentration less than the first semiconductor region (The first semiconductor region N+ is N+ doped, and thus has a higher dopant concentration than third semiconductor region INT, which is intrinsic, or undoped, silicon; see Fornara paragraph 0061).
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar, Chiu, and Huang.
In regard to claim 23, Fornara discloses a passive device including a first semiconductor region (N+ ion Fornara figure 1), a second semiconductor region (P+ in Fornara figure 1), and a third semiconductor region laterally extending between and directly contacting facing sidewalls of the first and second semiconductor regions along an entire height of each of the facing sidewalls (INT in Fornara figure 1);
Fornara does not disclose a backside contact. Fornara also does not explicitly recite a lack of a silicon substrate below the passive device, although Fornara also does not explicitly say that the substrate is silicon, and as such, if a non-silicon substrate is used, Fornara’s device would appear to meet this limitation.
Kar teaches another backside contact to the second semiconductor region of the passive device (122A in Kar figure 1A); and wherein there is no silicon substrate below the first and the second semiconductor region of the passive device (Kar describes the diodes as “substrate-less” [see paragraphs 0017 and 0022]. Furthermore, there is no silicon substrate depicted below the device in figure 1A). Kar also teaches that this allows for direct connection to the backside with potential resistance benefit (Kar paragraph 0023).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the backside contact of Kar in order to directly connect the passive device to the backside with potential resistance benefits.
Fornara does not disclose a transistor structure.
Chiu discloses a semiconductor structure comprising: a frontside (below 110B in Chiu figure 26A); a backside (above 110B in figure 26A); a transistor including a first and a second source/drain (110N2 and 110N3 in Chiu figure 26A) and a gate on the frontside (112N2 in Chiu figure 26A); a backside contact to the second source/drain region of the transistor(154 in Chiu figure 26A) wherein there is no silicon substrate below the first and the second source/drain and the gate of the transistor (Chiu paragraph 0050, the substrate is replaced by the ILD layer 142A. Furthermore, no silicon substrate is depicted on the backside of figure 26A);
The transistor and the passive device are completely disclosed by the aforementioned references, except neither reference combines both of them together. A transistor is a common component in nearly all electronics, and a diode-like passive device is often added into these for uses such as ESD protection (Kar paragraph 0023). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the transistor of Chiu with the passive device of Fornara.
Neither Fornara nor Chiu disclose that the passive device is orthogonal to the transistor.
Huang teaches the passive device is orthogonal to the transistor (in Huang figure 16, source fins 822, gate 810 and drain fins 824 form a transistor in direction, D1, and the diodes passive devices in direction D2. D1 and D2 are orthogonal to each other [paragraph 0066]). Huang teaches that this modified embodiment changes the direction in which current flows while maintaining being formed for bypassing the ESD currents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the combined devices of Fornara Kar and Chiu orthogonally to allow for a different current flow.
Furthermore, it has been found in previous court decisions that a simple rearrangement of parts that does not modify the operation of the device do not constitute a patentable limitation (See MPEP 2144.04 VI C, and In re Japikse, 181 F.2d 1019, 86 USPQ 70). In this case, the relative orientation of the elements as claimed has not been shown to change the operation of these separate devices, and thus it would be an obvious matter of rearranging the parts for any particular application.
Regarding claim 24, Fornara in view of Kar, Chiu, and Huang teach all of the limitations of claim 23. Fornara further discloses that the third semiconductor region is a semiconductor bridge laterally connecting the first and second semiconductor regions of the passive device (INT in Fornara figure 1).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Fornara in view of Kar, Chiu, and Huang as applied to claim 23 above, and further in view of Smith.
In regards to claim 25, Fornara in view of Kar, Chiu, and Huang teach all of the limitations of claim 23.
Fornara does not teach a pair of diffusion breaks located on either side of the passive device;
Smith teaches any suitable number of diffusion breaks (20 in Smith figure 4) to separate adjacent standard cells of a FET device (paragraph 0059). Smith also teaches that these prevent diffusion between the cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the diffusion breaks of Smith to the combined device of Fornara and Chiu in order to prevent diffusion between adjacent devices and separate adjacent devices.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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