Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3, 5-6, 9-10, 13, 16-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 19, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 14, 2023 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Figs. 1, 2, 3, 4, and 5 are not in compliance with MPEP §1.84(l). Specifically, "All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined."
Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Acronyms "PFET" and "NFET" are not explicitly defined in the specification.
Appropriate correction is required.
Claim Objections
Claim 2 is objected to because of the following informalities:
The limitation is missing "of" between "terminal connections" and "the second transistor".
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7-8, 19 are rejected under 35 U.S.C. 103 as being obvious over Chiang et al. (US12527081B2) in view of Zhang et al. (US11004856B1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Additionally, based on the publication date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(1).
Regarding Claim 1:
Chiang discloses a microelectronic structure (logic device; Fig. 4A), comprising:
a nanosheet transistor device stack (Fig. 4A, paragraph 25) having a first transistor device (element 400P) stacked (paragraph 61) on a second transistor device (element 400N), wherein:
the first transistor device (element 400P) includes a source and drain (elements 104P, paragraph 21); and
the second transistor device (element 400N) includes terminal connections (elements 104N, paragraph 21); and
a gate shared (element 402, paragraph 62) between the first transistor device (element 400P) and the second transistor device (element 400N).
However, Chiang does not explicitly teach wherein the first transistor device is configured to conduct a current nor where the terminal connections of the second transistor device are vestigial.
Zhang discloses an analogous stacked transistor memory cell (Fig. 4 element 200), wherein the first transistor device (Fig. 1 elements 102-1-4) is configured to conduct a current between the drain and the source (elements 222 and 224) based on a voltage on the gate (paragraph 21); and the terminal connections of the second transistor device are vestigial irrespective of a voltage applied to the gate, such that the second transistor device is always passive (paragraphs 20-22 and 37).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang further in view of Zhang to explicitly include where the first transistor device is configured to conduct a current between a corresponding drain and source based a voltage on the gate. Moreover, to include that the terminal connections of the second transistor device are vestigial such that the device is always passive because both are directed to analogous stacked transistor devices. Doing so enhances the performance and efficiency of field-effect transistors (Zhang, paragraphs 2 and 23).
Regarding Claim 2:
The combination of Chiang and Zhang disclose a microelectronic structure according to claim 1, but Chiang does not explicitly teach where the terminal connections of the second transistor are floating.
Zhang, however, discloses an analogous stacked transistor memory cell (Fig. 4 element 200), wherein the terminal connections of the second transistor device (Fig. 1 elements 140-2 and 140-3) are floating (paragraphs 20, 37, and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang further in view of Zhang to explicitly include a second transistor device with floating terminal connections because both are directed to analogous stacked transistor devices. Doing so improves the efficiency in the current flow while still allowing for an increase in structure density for transistor devices (Zhang, paragraphs 2 and 23).
Regarding Claim 4:
The combination of Chiang and Zhang disclose a microelectronic structure according to claim 1, wherein Chiang discloses the first transistor device (Fig. 4A element 400P) is a PFET (paragraph 61) and the second transistor device (element 400N) is an NFET (paragraph 61).
Regarding Claim 7:
The combination of Chiang and Zhang disclose a microelectronic structure according to claim 1, wherein Chiang discloses the first transistor device (Fig. 1A element 100N) is an NFET (paragraph 20) and the second transistor device (element 100P) is a PFET (paragraph 20).
Regarding Claim 8:
The combination of Chiang and Zhang disclose a microelectronic structure according to claim 7, but Chiang does not explicitly teach wherein the terminal connections of the second device are floating.
Zhang, however, discloses an analogous stacked transistor memory cell (Fig. 4 element 200), wherein the terminal connections of the second transistor device (Fig. 1 elements 140-2 and 140-3) are floating (paragraphs 20, 37, and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang further in view of Zhang to explicitly include a second transistor device with floating terminal connections because both are directed to analogous stacked transistor devices. Doing so improves the efficiency in the current flow while still allowing for an increase in structure density for transistor devices (Zhang, paragraphs 2 and 23).
Regarding Claim 19:
Chiang discloses a microelectronic structure (logic device; Fig. 4A), comprising:
a stacked nanosheet transistor (paragraph 25) that includes a first FET (Fig. 4 element 400P) and a second FET (element 400N); and
a gate shared (element 402, paragraph 62) by the first FET and the second FET.
However, Chiang does not explicitly teach wherein the first FET is always active and configured to conduct a current nor where the second FET is a vestigial device such that it is always passive.
Zhang discloses an analogous stacked transistor memory cell (Fig. 4 element 200), wherein the first FET is always active (Fig. 1 elements 102-1-4) and configured to pass a current between a drain and a source (elements 222 and 224) of the first FET based on a voltage on the gate (paragraph 21);
the second FET is a vestigial device (Fig. 1 elements 140-2 and 140-3) that is always passive (paragraphs 20-22 and 37); and
the second FET (Fig. 1 elements 140-2 and 140-3) includes terminal connections that are floating, grounded, or half-clamped (paragraph 20, 37, and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang further in view of Zhang to explicitly include where the first FET is always active and configured to pass a current between a corresponding drain and source based a voltage on the gate. Moreover, to include that the terminal connections of the second FET are floating, grounded, or half-clamped such that the device is vestigial and always passive because both are directed to analogous stacked transistor devices. Doing so enhances the performance and efficiency of field-effect transistors (Zhang, paragraphs 2 and 23).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claims 11-12, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US12527081B2) in view of Hwang et al. (US20200343886A1).
Regarding Claim 11:
Chiang discloses a microelectronic structure (logic device; Fig. 4A), comprising:
a nanosheet transistor device stack (paragraph 25) that includes:
an active field effect transistor (FET) (Fig. 4 element 400P) having a source and drain (elements 104P, paragraph 21); and
a gate shared (element 402, paragraph 62) by the active FET (element 400P) and the passive FET (element 400N).
However, Chiang does not explicitly teach a FET that is passive having terminal connections nor wherein the passive FET is configured to mitigate parasitic elements when the active FET is processing a signal.
Hwang discloses an analogous transistor circuit (Fig. 4 element 200) with a passive FET (element 270) having terminal connections (paragraph 66); wherein the active FET (element 220) is configured to actively process a signal (paragraphs 58-60) and the passive FET (element 270) is configured to mitigate parasitic elements when the active FET is processing the signal (paragraphs 26-27 and 57).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang further in view of Hwang to include a passive FET with terminals that is configured to mitigate parasitic elements – when the active FET is processing a signal – because both are directed to analogous transistor devices. Doing so prevents the processed signal from distortion due to nonlinearity or parasitic contributions (Hwang, paragraphs 3 and 4).
Regarding Claim 12:
The combination of Chiang and Hwang disclose a microelectronic structure according to claim 11, wherein Chiang discloses the active FET (Fig. 4A element 400P) is a PFET (paragraph 61) and the passive FET (element 400N) is an NFET (paragraph 61).
Regarding Claim 14:
The combination of Chiang and Hwang disclose a microelectronic structure according to claim 11, wherein Chiang discloses wherein the active FET (Fig. 1A element 100N) is an NFET (paragraph 20) and the passive FET (element 100P) is a PFET (paragraph 20).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US12527081B2) in view of Hwang et al. (US20200343886A1) as applied to claim 14 above, and further in view of Zhang et al. (US11004856B1).
Regarding Claim 15:
The combination of Chiang and Hwang disclose a microelectronic structure according to claim 14, but neither Chiang nor Hwang explicitly teach where the terminal connections of the passive FET are floating.
Zhang, however, discloses an analogous stacked transistor memory cell (Fig. 4 element 200) with a passive FET (Fig. 1 elements 140-2 and 140-3); wherein the terminal connections are floating (paragraphs 20, 37, and 44).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang and Hwang further in view of Zhang to explicitly include where the terminal connections of the passive FET are floating because both are directed to analogous transistor devices. Doing so enhances the performance and efficiency of field-effect transistors (Zhang, paragraphs 2 and 23).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US12527081B2) in view of Hwang et al. (US20200343886A1) as applied to claim 14 above, and further in view of Park et al. (US20230352528A1).
Regarding Claim 18:
The combination of Chiang and Hwang disclose a microelectronic structure according to claim 14, but neither Chiang nor Hwang explicitly teach wherein an effective width of the PFET is smaller than the NFET.
However, Park discloses an analogous multi-stack nanosheet structure (Fig. 6A element 10), wherein an effective width (Fig. 1A element W2) of the PFET (element 10U) is smaller (paragraph 39) than an effective width (element W1) of the NFET (element 10L, paragraph 45).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Chiang and Hwang further in view of Park to explicitly include where an effective width of a PFET is smaller than that of a NFET because both are directed to analogous stacked transistor devices. Doing so improves device performance and density (Park, paragraphs 4-7).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US12527081B2) in view of Zhang et al. (US11004856B1) as applied to claims 19 above, and further in view of Park et al. (US20230352528A1).
Regarding Claim 20:
The combination of Chiang and Zhang disclose a microelectronic structure according to claim 19, but neither explicitly teach wherein an effective width of the second FET is smaller than the first FET.
However, Park discloses an analogous multi-stack nanosheet structure (Fig. 6A element 10), wherein the second FET (element 10U) has an effective width (Fig. 1A element W2) that is smaller (paragraph 39) than an effective width (element W1) of the first FET (element 10L, paragraph 45).
It would have been obvious to one of ordinary skill before effective filing date of the claimed invention to modify the structure described in Chiang and Zhang further in view of Park to explicitly include where an effective width of the second FET is smaller than that of a first FET because both are directed to analogous stacked transistor devices. Doing so improves device performance and density (Park, paragraphs 4-7).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ikeda et al. (CN 113875152 A), You et al. (US 6937086 B1), Rogers et al. (US 11521962 B1), Zhou et al. (US 20250098329 A1).
Conclusion
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/Chloë E Benton/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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