Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 5/26/2026 is acknowledged.
Claims 18-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention of Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/26/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 15th, 2023 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Multi-depth Contacts Plugs extending through Enlarged Pad Regions in Semiconductor Devices.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US11164886B2) in view of Kim et al. (US11637121B2).
Regarding Claim 1:
Baek discloses a semiconductor device (Fig. 5) comprising:
a first gate structure (Fig. 4 element GGE2) including stacked first selection lines (Fig. 13A elements GGE2a-b), each first selection line (Fig. 2, paragraph 23) including a first cell region (Fig. 14 element EP) and a first pad region (element PAD) adjacent in a first direction (D1);
a second gate structure (Fig. 4 element GGE1) including stacked second selection lines (Fig. 10 elements GGE1a-b), each second selection line (Fig. 2, paragraph 23) including a second cell region (Fig. 14 element EP) and a second pad region (element PAD) adjacent in the first direction;
first contact plugs (Figs. 10-13B element PLG) extending through the first pad region (element PAD) and respectively connected to the first selection lines (elements GGE2a-b);
and second contact plugs (Figs. 7-13A element PLG) extending through the second pad region (element PAD) and respectively connected to the second selection lines (elements GGE1a-b),
wherein in a second direction (D2) crossing the first direction (D1), the first pad region has a width greater than that of the first cell region (paragraph 101).
However, Baek does not explicitly disclose where the second pad region has a greater width than the first pad region.
Kim discloses an analogous semiconductor memory device (Fig. 1) with pad regions (Figs. 7-8D) in a connection region (CNR1) where the second pad region (Fig. 4 element W2) has a width greater (paragraph 37) than that of the first pad region (element W3) in a second direction (Y).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek further in view of Kim to explicitly include wherein a second direction, the second pad region has a width greater than that of the first pad region because both are directed to analogous semiconductor devices. Doing so improves the efficiency of the manufacturing process of these highly integrated semiconductor devices (Kim, paragraphs 2-4).
Regarding Claim 2:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, wherein Baek further discloses the first pad region (Fig. 14 elements GGE2/PAD) is disposed between the first cell region (element EP) and the second pad region (elements GGE1/PAD).
Regarding Claim 3:
The combination of Baek and Kim disclose a semiconductor device according to claim 2, wherein Baek further discloses the first pad region (Fig. 14 elements GGE2/PAD) protrudes between (paragraph 112) the second cell region (elements GGE1/EP) and the second pad region (element PAD).
Regarding Claim 4:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, wherein Baek further discloses the first pad region (Fig. 14 elements GGE2/PAD) and the second pad region (elements GGE1/PAD) are adjacent in the first direction (D1).
Regarding Claim 5:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, wherein Baek further discloses the second gate structure (Figs. 4 and 14 element GGE1) includes a connection region (element LP) connecting (paragraph 35) the second cell region (element EP) and the second pad region (element PAD), and wherein the first pad region protrudes (Fig. 14 in D2) toward the connection region.
Regarding Claim 6:
The combination of Baek and Kim disclose a semiconductor device according to claim 5, wherein Baek further discloses the first pad region (Fig. 14 element GGE2/PAD) protrudes (paragraph 112) into the second gate structure (element GGE1), and wherein the second cell region (EP), the connection region (LP), and the second pad region (PAD) surround the first pad region (See Fig. 14).
Regarding Claim 7:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, wherein Baek further discloses an isolation structure (Figs 5 and 6D elements ESS1/2) extending between the first gate structure and the second gate structure (paragraph 111).
Claims 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US11164886B2) in view of Kim et al. (US11637121B2) as applied to claim 1 above, and further in view of Oike et al. (US20190371813A1).
Regarding Claim 8:
The combination of Baek and Kim disclose a semiconductor device according to claim 1 with first and second gate structures, but neither Baek nor Kim explicitly disclose a dummy gate structure or an isolation structure that specifically isolates the dummy gate structure from the first and second gate structures.
Oike, however, discloses an analogous semiconductor memory device (Fig. 1), further comprising a dummy gate structure (Fig. 10, element DBLK) including stacked dummy selection lines (Figs. 9/12 elements SGDa-c); and an isolation structure (elements SLT) electrically isolating the first gate structure (element SU1), the second gate structure (element SU0), and the dummy gate structure (element DBLK) from each other (paragraph 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek and Kim further in view of Oike to explicitly include a dummy gate structure – with stacked dummy selection lines – electrically isolated from the first and second gate structures because both are directed to analogous semiconductor devices. Doing so enhances the structural integrity and the overall efficiency of the semiconductor device (Oike, paragraph 81).
Regarding Claim 9:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 8, wherein Baek further discloses the isolation structure comprises: a first line portion (Fig. 13A element LSP) extending (paragraphs 64 and 69-70) between the first gate structure (element GGE2) and the second gate structure (GGE1) and including a bending portion (Fig. 14). However, neither Baek nor Kim explicitly discloses a second line portion extending between the second gate structure and the dummy gate structure.
Oike discloses an analogous semiconductor memory device (Fig. 1), comprising a line portion (Fig. 10 element SLT) extending between the second gate structure (element SU0) and the dummy gate structure (DBLK).
PNG
media_image1.png
585
611
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek and Kim further in view of Oike to explicitly include a second line portion extending between the second gate structure and a dummy gate structure because both are directed to analogous semiconductor devices. Doing so enhances the structural integrity and the overall efficiency of the semiconductor device (Oike, paragraph 81).
Regarding Claim 10:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 9, wherein Baek further discloses the first line portion (Figs. 13A and 14 element LSP) comprises: a straight line portion (see annotated fig. attached below) extending between the first cell region (element GGE2/EP) and the second cell region (GGE1/EP); and the bending portion extending between the first pad region (element GGE2/PAD) and the second pad region (element GGE1/PAD).
PNG
media_image2.png
585
611
media_image2.png
Greyscale
Regarding Claim 11:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 8, comprising a first gate structure, a second gate structure, a dummy gate structure, and an isolation structure, however neither Baek nor Oike explicitly teach a third gate structure disposed under the structures mentioned above.
Kim, however, discloses an analogous semiconductor memory device (Fig. 1) further comprising: a third gate structure (see annotated fig. attached below) including stacked gate lines (elements DWL/WL) disposed under first and second stacked selection lines (elements SSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek, Kim, and Oike further in view of Kim to explicitly include a third gate structure – with stacked gate lines – disposed under the isolation structure and the first, second, and dummy gate structures because both are directed to analogous semiconductor devices. Doing so improves the efficiency of these highly integrated semiconductor devices (Kim, paragraphs 2-4).
PNG
media_image3.png
606
524
media_image3.png
Greyscale
Regarding Claim 12:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 11, but neither Baek nor Kim explicitly disclose contact plugs extending through the dummy gate structure and the third gate structure, respectively connected to gate lines.
Oike discloses an analogous semiconductor memory device (Fig. 1), further comprising: third contact plugs (Figs. 10 and 12 elements CC) extending through the dummy gate structure (element DBLK) and respectively connected to the gate lines (elements WL).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek, Kim, and Oike further in view of Oike to explicitly include third contact plugs extending through a dummy gate structure and a third gate structure – respectively connected to gate lines – because both are directed to analogous semiconductor devices. Doing so enhances the structural integrity and the overall efficiency of the semiconductor device (Oike, paragraph 81).
Regarding Claim 13:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 12, wherein Baek further discloses a fourth contact plug (Fig. 6A-B elements PLG) extending through the first gate structure (element GGE2), wherein the fourth contact plug (element PLG) is connected to an uppermost gate line (Fig. 2 element DWL, paragraphs 72 and 78-79). However, neither Baek nor Oike explicitly teach where the fourth contact plug extends through the third gate structure.
Kim discloses an analogous semiconductor memory device (Fig. 1) comprising a third gate structure (see annotated fig. attached above) and contact plugs (Fig. 6 element CT1/2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek, Kim, and Oike further in view of Kim to explicitly include a fourth contact plug – extending through the first gate structure and a third gate structure – connected to an uppermost gate line because both are directed to analogous semiconductor devices. Doing so improves the efficiency of these highly integrated semiconductor devices (Kim, paragraphs 2-4).
Regarding Claim 14:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 13, wherein Baek further discloses the uppermost gate line is a dummy word line (Fig. 2 element DWL, paragraphs 72).
Regarding Claim 15:
The combination of Baek, Kim and Oike disclose a semiconductor device according to claim 13, wherein Baek further discloses a fifth contact plug (Fig. 6A-B elements PLG) extending through the second gate structure (element GGE1), wherein the fifth contact plug (element PLG) is connected to an uppermost gate line (Fig. 2 element DWL, paragraphs 72 and 78-79). However, neither Baek nor Oike does not explicitly teach where the fifth contact plug extends through the third gate structure.
Kim, however, discloses an analogous semiconductor memory device (Fig. 1) comprising a third gate structure (see annotated fig. attached above) and contact plugs (Fig. 6 element CT1/2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device described in Baek, Kim, and Oike further in view of Kim to explicitly include a fifth contact plug – extending through the second gate structure and a third gate structure – connected to the uppermost gate line because both are directed to analogous semiconductor devices. Doing so improves the efficiency of these highly integrated semiconductor devices (Kim, paragraphs 2-4).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US11164886B2) in view of Kim et al. (US11637121B2) as applied to claim 1 above, and further in view of Baek et al. (US20200194373A1), hereinafter referred to as "Baek '373".
Regarding Claim 16:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, but neither Baek nor Kim explicitly disclose first supports or second support extending through the first and second pad regions, respectively.
However, Baek ‘373 discloses an analogous semiconductor memory device (Fig. 3), comprising first supports (Fig. 7 elements 80D) extending through the first pad region (element 72BP) and disposed around the first contact plugs (element 127); and second supports (elements 80D) extending through the second pad region (element 72AP) and disposed around the second contact plugs (element 127, paragraph 60).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device described in Baek and Kim further in view of Baek ‘373 to explicitly include first and second supports extending through respective pad regions and surrounding respective contact plugs because both are directed to analogous semiconductor devices. Doing allows for major increases in integration density while maintaining the structural integrity (Baek ‘373, paragraphs 3-4).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US11164886B2) in view of Kim et al. (US11637121B2) as applied to claim 1 above, and further in view of Jung et al. (US20210202520A1).
Regarding Claim 17:
The combination of Baek and Kim disclose a semiconductor device according to claim 1, but neither Baek nor Kim explicitly disclose the first or second contact plugs being surrounded by insulating spacers.
However, Jung discloses an analogous semiconductor device (Fig. 2), comprising insulating spacers (element 176) respectively surrounding sidewalls of contact plugs (Figs. 3 and 7 elements 184).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device described in Baek and Kim further in view of Jung to explicitly include insulating spacers surrounding sidewalls of the first and second contact plugs, respectively, because both are directed to analogous semiconductor devices. Doing so improves the electrical characteristic of semiconductor device while allowing for an increase in density (Jung, paragraphs 3-4).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Im et al. (US 20220130430 A1), Lee et al. (US 20200227434 A1), Kim et al. (KR 20200000241 A), Lee et al. (U 20160343434 A1), Kim et al. (US 20180247940 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
Prosecution Insights