Radio frequency amplification circuit capable of operating in multiple gain modes

Application No. 18/540,894

• Filed: Dec 15, 2023
• Examiner: ALAM, FAYYAZ
• Art Unit: 2646
• Tech Center: 2600 — Communications
• Assignee: Richwave Technology Corp.
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.

Information Disclosure Statement
The information disclosure statement submitted has been considered by the Examiner and made of record in the application file.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.

Claim(s) 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee USPN 2018/0248526.
Consider claim 1, Lee discloses a radio frequency (RF) amplification circuit, comprising: an input terminal configured to receive an RF input signal (see fig. 5D: 511); an output terminal configured to provide an RF output signal (see fig. 5D: 519); an amplification path coupled between the input terminal and the output terminal and comprising an amplifier (see fig. 5D: 520); and a bypass path coupled in parallel with the amplification path between the input terminal and the output terminal (see fig. 5D: 530), and comprising: a first bypass switch (see fig. 5D: 535); a first node located between the input terminal and the first bypass switch (see fig. 5D); a second node located between the first node and the first bypass switch (see fig. 5D); a first wiring segment disposed between the first node and the second node (see fig. 5D); and a first variable capacitive structure disposed between the first node and the second node and comprising a first capacitive element and a first switching element (see fig. 5D: 545).

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Allowable Subject Matter
Claim 20 is allowed.
Claims 2-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: respective claimed recitations.

Conclusion
Any response to this Office Action should be faxed to [phone] or mailed to:
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Hand-delivered responses should be brought to
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Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Fayyaz Alam whose telephone number is [phone]. The Examiner can normally be reached on Monday-Friday from 9:30am to 7:00pm.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Oneal Mistry can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist/customer service whose telephone number is [phone].

Fayyaz Alam

February 18, 2026

/FAYYAZ ALAM/
Primary Examiner, Art Unit 2674

Prosecution Timeline

• Dec 15, 2023: Application Filed
• Feb 18, 2026: Non-Final Rejection — §102 (current)