DETAILED ACTION
This action is responsive to the following: the amendments and the arguments made in amendment filed on November 26, 2025.
Claims 1-20 are pending. Claims 1, 13, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on November 26, 2025 have been entered. Claims 1-20 remain pending. The amendments overcome the objections set forth in the previous office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-10, 12-13, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fantini et al. (US 20190295610) in view of Choi et al. (US 6009040).
Regarding Independent Claim 1, Fantini teaches An operating method of a memory system (Fig. 1A: 100), comprising:
inputting tracking data (para 32; “In some examples, tracking memory cells 120-1 may be updated (e.g., rewritten) each time memory cells 120-2 are written”) into a tracking array (Fig. 1A: 114);
generating a plurality of tracking logic values by a plurality of tracking cell columns in the tracking array according to the tracking data (para 59);
counting the plurality of tracking logic values to generate a summation value (para 60; “ISUM”);
performing a computing operation by a computing array to generate a plurality of computing signals (para 62; “read the memory cells”); and
sensing the plurality of computing signals by the sensing device (para 43; “memory cells may be sensed”).
However, Fantini fails to teach adjusting a sensing time of a sensing device according to the summation value; and a clock signal: when the summation value is different from a preset value, adjusting a period of the clock signal.
Choi teaches adjusting the sensing time of a sensing device using the information from a tracking array (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
a clock signal (Fig. 10: P1, P2, Pm):
and when the summation value is different from a preset value, adjusting a period of the clock signal. (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”; Fig 10: )
Choi states ”the times needed for sufficient charge transfer to sense the respective data states of the differently programmed cells may differ. At one extreme, using a sensing time based on the "00" state may provide insufficient time for charge transfer to sense the "01" and "10" states, potentially leading to data sensing errors. At another extreme, however, use of a sensing time based on the "10" state may increase data access time and current consumption, leading to reduced reliability and shortened battery lifetime in low-power applications.” (col 2 line 67, col 3 lines 1-9) Thus there is an obvious advantage to having a sensing scheme when sensing currents from cells to use the minimum duration necessary to enable charge transfer without increasing power consumption.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed in invention to apply the teachings of Fantini to the teachings of Choi to produce a method of adjusting the sensing of time of a memory system by using the summed information from a tracking array in order to sense computing signals.
Regarding Claim 2, Fantini and Choi teach the limitations of Claim 1. Fantini teaches wherein adjusting the sensing device according to the summation value (para 60; “ISUM”) comprises:
comparing (Fig. 8A: 834) the summation value (para 60; “ISUM”) and a quantity of the plurality of tracking cell columns;
when the summation value is different from the quantity of the plurality of tracking cell columns, adjusting the sensing; and
when the summation value is equal to the quantity of the plurality of tracking cell columns, determining the sensing (para 73).
Choi teaches that adjusting the sensing time (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
Choi states ”the times needed for sufficient charge transfer to sense the respective data states of the differently programmed cells may differ. At one extreme, using a sensing time based on the "00" state may provide insufficient time for charge transfer to sense the "01" and "10" states, potentially leading to data sensing errors. At another extreme, however, use of a sensing time based on the "10" state may increase data access time and current consumption, leading to reduced reliability and shortened battery lifetime in low-power applications.” (col 2 line 67, col 3 lines 1-9) Thus there is an obvious advantage to having a sensing scheme when sensing currents from cells to use the minimum duration necessary to enable charge transfer without increasing power consumption.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed in invention to apply the teachings of Fantini to the teachings of Choi to produce a method of adjusting the sensing of time of a memory system by comparing the summation values to the quantity of tracking cells from a tracking array in order to sense computing signals.
Regarding Claim 3, Fantini and Choi teach the limitations of Claim 1. Fantini further teaches further comprising:
generating a plurality of tracking signals (para 54; “A sensing voltage may be determined from a leakage current through the tracking memory cells”) according to the tracking data by the plurality of tracking cell columns (Fig. 8A: TRACKING CELLS);
counting the plurality of first tracking logic values to generate a first summation value (Fig. 8A: ISUM); and
when the first summation value is equal to a quantity of the plurality of tracking cell columns, adjusting sensing values (para 73)
However, Fantini fails to teach setting the sensing time as a first and second sensing time; wherein the second sensing time is smaller than the first sensing time.
Choi teaches adjusting the sensing time of a sensing device using the information from a tracking array time (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 4, Fantini and Choi teach the limitations of Claim 3. Fantini further teaches sensing the plurality of tracking signals according to the to generate a plurality of second tracking logic values (para 73);
counting the plurality of second tracking logic values to generate a second summation value (Fig. 8A: ISUM);
when the second summation value (Fig. 8A: ISUM) is different from the quantity of the plurality of tracking cell columns (para 73),
However, Fantini fails to teach a sensing time.
Choi teaches setting the sensing time as the first sensing time (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”); and
sensing the plurality of computing signals according to the first sensing time by the sensing device (Fig. 7: 180).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 5, Fantini and Choi teach the limitations of Claim 4. Choi further teaches sensing the plurality of tracking signals according to the second sensing time to generate a plurality of second tracking logic values (para 73);
counting the plurality of second tracking logic values to generate a second summation value (Fig. 8A: ISUM);
when the second summation value (Fig. 8A: ISUM) is different from the quantity of the plurality of tracking cell columns adjusting the sensing (para 73); and
sensing the plurality of computing signals according (para 43; “memory cells may be sensed”)
Choi teaches adjusting the sensing time of a sensing device using the information from a tracking array (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 7, Fantini and Choi teach the limitations of Claim 1. Fantini further teaches further comprising:
generating a plurality of tracking signals (para 54; “A sensing voltage may be determined from a leakage current through the tracking memory cells”) according to the tracking data by the plurality of tracking cell columns (Fig. 8A: TRACKING CELLS);
counting the plurality of first tracking logic values to generate a first summation value (Fig. 8A: ISUM); and
when the first summation value is different to a quantity of the plurality of tracking cell columns, adjusting sensing values (para 73)
However, Fantini fails to teach setting the sensing time as a first and second sensing time; wherein the second sensing time is smaller than the first sensing time.
Choi teaches adjusting the sensing time of a sensing device using the information from a tracking array(Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 8, Fantini and Choi teach the limitations of Claim 7. Fantini teaches further comprising:
counting the plurality of second tracking logic values to generate a second summation value (Fig. 8A: ISUM); and
when the second summation value is equal to the quantity of the plurality of tracking cell columns (para 73),
However, Fantini fails to teach setting the sensing time as a third sensing time,
wherein the third sensing time is larger than the second sensing time.
Choi teachings adjusting the sensing time and different sensing times of different magnitudes (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 9, Fantini and Choi teach the limitations of Claim 8. Fantini further teaches further comprising:
counting the plurality of second tracking logic values to generate a third summation value (Fig. 8A: ISUM);
when the third summation value (Fig. 8A: ISUM) is equal to the quantity of the plurality of tracking cell columns (para 73)
However, Fantini fails to teach setting the sensing time as the second sensing time; and
sensing the plurality of computing signals according to the second sensing time by the sensing device.
Choi teachings adjusting the sensing time and different sensing times of different magnitudes. (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”)
The rationale for combining the references is the same as Claim 1.
Regarding Claim 10, Fantini and Choi teach the limitations of Claim 9. Fantini teaches a predetermined sensing value that can be adjusted based on the information in a tracking array (Para 46; “sensing voltage VDM may be predetermined and fixed”).
Choi teaches adjusting a sensing time based on the values in a tracking array (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 1.
Regarding Claim 12, Fantini and Choi teach the limitations of Claim 1. Fantini teaches wherein each of tracking bits of the tracking data has the same logic value (para 54; “The tracking page may be programmed to a tracking pattern of all 1s or may be programmed to include a split of 1s and 0s.”).
The rationale for combining the references is the same as Claim 1.
Regarding Independent Claim 13, Fantini teaches a memory system (Fig. 1A: 100), comprising:
a plurality of tracking cell columns (Fig. 1A: 114) configured to generate a plurality of tracking logic values according to tracking data (para 32; “In some examples, tracking memory cells 120-1 may be updated (e.g., rewritten) each time memory cells 120-2 are written”);
a computing array (Fig. 1A: 110) configured to generate a plurality of computing signals; and
a sensing device (para 26 “read memory cells from array 110 using the sensing voltage.”) configured to sense the plurality of computing signals according to a clock signal,
wherein the sensing device (para 26 “read memory cells from array 110 using the sensing voltage.”) comprises a segment circuit (Fig. 8A: 830) configured to count the plurality of tracking logic values to generate a summation value (Fig. 8A: ISUM),
However, Fantini fails to teach when the summation value is different from a preset value, a period of the clock signal is adjusted, and
when the summation value is equal to preset value, the period of the clock signal is determined for sensing the plurality of computing signals.
Choi teaches adjusting the period of a clock signal used in sensing computing signals (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
Choi states ”the times needed for sufficient charge transfer to sense the respective data states of the differently programmed cells may differ. At one extreme, using a sensing time based on the "00" state may provide insufficient time for charge transfer to sense the "01" and "10" states, potentially leading to data sensing errors. At another extreme, however, use of a sensing time based on the "10" state may increase data access time and current consumption, leading to reduced reliability and shortened battery lifetime in low-power applications.” (col 2 line 67, col 3 lines 1-9) Thus there is an obvious advantage to having a sensing scheme when sensing currents from cells to use the minimum duration necessary to enable charge transfer without increasing power consumption.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed in invention to apply the teachings of Fantini to the teachings of Choi to produce a method of adjusting the period of a clock signal of a memory system by using the summed information from a tracking array in order to sense computing signals.
Regarding Claim 14, Fantini and Choi teach the limitations of Claim 13. Fantini teaches wherein reference data bits (para 61 “Different configuration patterns correspond to different sensing voltages and may include various combinations of binary bits”) stored in each tracking cell column of the plurality of tracking cell columns has P first logic value, and P is a positive integer.
The rationale for combining the references is the same as Claim 13.
Regarding Independent Claim 18, Fantini teaches an operating method of a memory system (Fig. 1A: 100), comprising:
counting a plurality of tracking logic values to generate a summation value (Fig. 8A: ISUM);
comparing the summation value with a preset value (Fig. 8A: 834; para 73);
performing a computing operation (para 62; “read the memory cells”) and sensing a plurality of computing signals from the computing operation according to the clock signal.
However, Fantini fails to teach when the summation value is different from the preset value, adjusting a period of a clock signal;
when the summation value is equal to the preset value, determining the period;
Choi teaches adjusting the period of a clock signal used in sensing computing signals. (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”)
Choi states ”the times needed for sufficient charge transfer to sense the respective data states of the differently programmed cells may differ. At one extreme, using a sensing time based on the "00" state may provide insufficient time for charge transfer to sense the "01" and "10" states, potentially leading to data sensing errors. At another extreme, however, use of a sensing time based on the "10" state may increase data access time and current consumption, leading to reduced reliability and shortened battery lifetime in low-power applications.” (col 2 line 67, col 3 lines 1-9) Thus there is an obvious advantage to having a sensing scheme when sensing currents from cells to use the minimum duration necessary to enable charge transfer without increasing power consumption.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed in invention to apply the teachings of Fantini to the teachings of Choi to produce a method of adjusting the period of a clock signal of a memory system by using the summed information from a tracking array in order to sense computing signals.
Regarding Claim 19, Fantini and Choi teach the limitations of Claim 18.
Fantini further teaches counting tracking cell values (Fig. 8A: 830) to produce a summation value (Fig. 8A: ISUM).
However, Fantini fails to teach sensing times and adjusting sensing times.
Choi teaches further comprising:
during a first period (Fig. 11: t1), operating the clock signal (Fig. 4: CLK) by a first sensing time (Fig. 11: t1) to generate a plurality of first tracking logic values;
during a second period (Fig. 11: t2), operating the clock signal by a second sensing time (Fig. 11: t2) to generate a plurality of second tracking logic values; and
wherein the first period is before the second period, and the first sensing time is larger than the second sensing time (col 7 lines 57-60; “Each of the clock dividers 284-288 generates a clock signal Pi (i=1-m) having a period twice that of the clock signal input thereto from a previous clock divider stage”; Though Choi teaches doubling the period of the sensing time, it would represent an obvious variant to instead reduce the period, such as by halving. As circuits that manipulate the frequency/period of a clock signal are well understood in the art.).
Regarding Claim 20, Fantini and Choi teach the limitations of Claim 19. Fantini teaches further comprising:
in response to the first summation value (Fig. 8A: ISUM) being equal to the preset value (Fig. 8A: 834; para 73) and the second summation value (Fig. 8A: ISUM) being different from the preset value (Fig. 8A: 834; para 73),
However, Fantini fails to teach sensing the plurality of computing signals according to the first sensing time.
Choi teaches a adjusting the sensing time for read operations based on the values in a tracking array (Col 3 lines 23-24; “a sensing period that has a duration controlled based on current generated in the dummy memory cell.”).
The rationale for combining the references is the same as Claim 19.
Allowable Subject Matter
Claims 6, 11, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 requires the difference between the initial sensing time and the third sensing time is the same as the difference between the first and second sensing time. Neither Fantini nor Choi teaches the difference between different sensing times are the same as differences between other sensing times. Thus, the claim is allowable.
Claim 11 requires the difference between the initial sensing time and the fourth sensing time is the same as the difference between the first and second sensing time. Neither Fantini nor Choi teaches the difference between different sensing times are the same as differences between other sensing times.
Claim 15, teaches an increasing a tracking logic value along a direction of the array. Neither Choi nor Fantini teach a relationship between the position in the array and the values stored in the tracking array. Thus, limitations of claim 15 is allowable.
Claim 17, teaches a preset value that is determined by the number of tracking columns. Nether Fantini not Choi teach a preset value that is based on the number of tracking column. Thus claim 17 is allowable.
Response to Amendment
Applicant's arguments filed November 26, 2025 have been fully considered but they are not persuasive.
Applicant’s arguments deal primarily with Independent Claims 1, 13 and 18 and argue that because Choi doesn’t teach a signal called clock or CLK that is adjusted to change sensing windows in the memory during a sensing operation.
Choi does teach several clock signals, Pi, as shown in Figure 10, that are generated from a master clock signal CLK and Fg00 and Fg01, which are generated from the current in in dummy memory cells. The differences in the Fg00 and Fg01 signals changes the sensing times generated for sensing cells in the array.
For this reason, the rejections of Independent Claims 1, 13, and 18 are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825