CTNF 18/541,034 CTNF 96519 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 11 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Wimer (2014, “A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops) . Regarding claim 1, Wimer teaches a system, comprising: first digital components clocked by a system clock signal (components clocked by clk, Fig. 6-7, Section II: Auto-Gated Flip-Flops); second digital components clocked by a gated system clock signal (components clocked by clk_g, Figs. 6-7, Section II: Auto-Gated Flip-Flops); a detection module configured to detect a detection event and produce an event flag signal upon said detection (FF’, Fig. 6, Section II: Auto-Gated Flip-Flops); and clock gating circuitry configured to generate a synchronous timing window during which gating of the gated system clock signal is released so that it follows the system clock signal in response to the event flag signal, but to otherwise gate the gated system clock signal such that it does not pulse (Fig. 7, clk_g follows clk; Section II: Auto-Gated Flip-Flops). Regarding claim 11, Wimer teaches a method of clocking a system, comprising: clocking first digital components with a system clock signal (components clocked by clk, Fig. 6-7, Section II: Auto-Gated Flip-Flops); clocking second digital components with a gated system clock signal (components clocked by clk_g, Figs. 6-7, Section II: Auto-Gated Flip-Flops); detecting a detection event and generating an event flag signal based upon said detection (FF’, Fig. 6, Section II: Auto-Gated Flip-Flops); and generating a synchronous timing window during which gating of the gated system clock signal is released so that it follows the system clock signal in response to the event flag signal, but otherwise gating the gated system clock signal such that it does not pulse (Fig. 7, clk_g follows clk; Section II: Auto-Gated Flip-Flops) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wimer (2014, “A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops) in view of Tsai US 20210173053 A1 . Regarding claim 2, Wimer teaches the system of claim 1, Wimer does not explicitly teach further comprising a light source configured to emit ranging light toward a target; and wherein the clock gating circuitry is configured to also gate the gated system clock signal when the light source is not activated. Tsai teaches emitting ranging light, and clocking system which gate components when the light source is not activated (pulsed laser source 10 and clock clk2 associated with the laser pulse clock clk1 and pulse width such that it would be inactive when laser is inactive, Fig. 1, [0031-33, 66-69]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wimer to include comprising a light source configured to emit ranging light toward a target; and wherein the clock gating circuitry is configured to also gate the gated system clock signal when the light source is not activated similar to Tsai with a reasonable expectation of success. This would have the predictable result of saving energy between laser emissions. Regarding claim 10, Wimer teaches the system of claim 1, Wimer does not explicitly teach wherein the system is configured to define a time-of-flight system and further comprises: a light source configured to emit ranging light toward a target; and a detector configured to detect ranging light that has reflected off the target and returned to the system to generate the detection event. Tsai teaches emitting ranging light, detecting returned light, and generating clocking system which gate components when the light source is not activated (pulsed laser source 10, light receiving unit 11 which generates digital, Fig. 1, [0031-33, 66-69]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wimer such that the system is configured to define a time- of-flight system and further comprises: a light source configured to emit ranging light toward a target; and a detector configured to detect ranging light that has reflected off the target and returned to the system to generate the detection event similar to Tsai with a reasonable expectation of success. This would have the predictable result of saving energy between laser emissions. Regarding claim 12, Wimer teaches the method of claim 11, Wimer does not explicitly teach further comprising also gating the gated system clock signal when a light source that emits ranging light toward a target is not activated. Tsai teaches emitting ranging light, and clocking system which gate components when the light source is not activated (pulsed laser source 10 and clock clk2 associated with the laser pulse clock clk1 and pulse width such that it would be inactive when laser is inactive, Fig. 1, [0031-33, 66-69]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wimer to include also gating the gated system clock signal when a light source that emits ranging light toward a target is not activated similar to Tsai with a reasonable expectation of success. This would have the predictable result of saving energy between laser emissions . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 3-9 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not explicitly teach or render obvious the system of claim 1 or method of claim 11 , specifically including: the clock gating circuitry comprises: a digital comparator configured to generate a comparator output signal based upon a comparison of a count value with a threshold value, wherein the comparator output signal is asserted by the digital comparator when the count value is less than the threshold value and is deasserted by the digital comparator when the count value is equal to or greater than the threshold value; a counter configured to: set the count value to a pre-determined value upon receipt of the event flag signal; and in response to the comparator output signal being asserted, increment the count value upon each successive rising edge of the system clock signal after the event flag signal is asserted, but to cease incrementing of the count value when the comparator output signal is deasserted; and a clock gating module configured to: release gating of the gated system clock signal such that it follows the system clock signal, a first given number of cycles of the system clock signal after assertion of the comparator output signal; and reinstate gating of the gated system clock signal such that it does not pulse, a second given number of cycles of the system clock signal after the release of the gating; wherein the threshold value is equal to the second given number of cycles. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C FRITCHMAN whose telephone number is (571)272-5533. The examiner can normally be reached M-F 8:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Isam Alsomiri can be reached on 571-272-6970. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.C.F./Examiner, Art Unit 3645 /ISAM A ALSOMIRI/Supervisory Patent Examiner, Art Unit 3645 Application/Control Number: 18/541,034 Page 2 Art Unit: 3645 Application/Control Number: 18/541,034 Page 3 Art Unit: 3645 Application/Control Number: 18/541,034 Page 4 Art Unit: 3645 Application/Control Number: 18/541,034 Page 5 Art Unit: 3645 Application/Control Number: 18/541,034 Page 6 Art Unit: 3645 Application/Control Number: 18/541,034 Page 7 Art Unit: 3645
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