DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US 2021/0325714).
As to claim 1, Shin discloses in figures 2 and 4B, an array substrate, comprising: a substrate 111; a first signal line comprising a first line segment 170 and a second line segment, wherein the first line segment is disposed on the substrate, and the second line segment comprises a connection portion 131 and a wiring portion 151; a first insulation layer 112 covering the substrate and the first line segment, wherein at least one first via hole is defined in the first insulation layer; a second signal line (adjacent to the first signal line) comprising a third line segment 151, wherein the third line segment and the second line segment are located in a same layer and are disposed adjacently on the first insulation layer 112, the connection portion 131 is connected to the first line segment 170 through the first via hole and overlaps the first line segment 170, and the wiring portion 151 is connected to the connection portion 131; a second insulation layer 113 covering the first insulation layer, the third line segment, and the second line segment; and a barrier wall 300 disposed on a side of the second insulation layer away from the substrate and intersecting the third line segment; wherein in an orthographic projection pattern of the array substrate, a boundary of the barrier wall does not simultaneously cover the connection portion and the third line segment.
As to claim 2, Shin discloses all of the elements of the claimed invention discussed above regarding claim 1. Shin further discloses in figure 2, wherein in the orthographic projection pattern of the array substrate, and the barrier wall is located on an outer periphery of the second line segment.
As to claim 3, Shin discloses all of the elements of the claimed invention discussed above regarding claim 2. Shin further discloses in figures 8 and 9, a barrier wall 400 located on an outside of the first line segment away from the second line segment.
As to claim 5, Shin discloses all of the elements of the claimed invention discussed above regarding claim 2. Shin further discloses in figure 2, wherein a distance between the wiring portion 151 and the third line segment 151 is greater than a distance between the connection portion 130 and the third line segment 151.
As to claim 15, Shin discloses all of the elements of the claimed invention discussed above regarding claim 1. Shin further discloses in figure 4A, wherein the array substrate further comprises a planarization layer 114, material of the planarization layer is organic material, the planarization layer covers the second insulation layer 113, and the barrier wall is disposed on a side of the planarization layer away from the substrate.
As to claim 16, Shin discloses in figures 2, 4A and 4B, a display panel 100, comprising an opposite substrate 120, a liquid crystal layer 150, and an array substrate 110, wherein the liquid crystal layer is disposed between the opposite substrate and the array substrate, wherein the array substrate comprises: a substrate 111; a first signal line comprising a first line segment 170 and a second line segment, wherein the first line segment is disposed on the substrate, and the second line segment comprises a connection portion 131 and a wiring portion 151; a first insulation layer 112 covering the substrate and the first line segment, wherein at least one first via hole is defined in the first insulation layer; a second signal line (adjacent to the first signal line) comprising a third line segment 151, wherein the third line segment and the second line segment are located in a same layer and are disposed adjacently on the first insulation layer 112, the connection portion 131 is connected to the first line segment 170 through the first via hole and overlaps the first line segment 170, and the wiring portion 151 is connected to the connection portion 131; a second insulation layer 113 covering the first insulation layer, the third line segment, and the second line segment; and a barrier wall 300 disposed on a side of the second insulation layer away from the substrate and intersecting the third line segment; wherein in an orthographic projection pattern of the array substrate, a boundary of the barrier wall does not simultaneously cover the connection portion and the third line segment.
As to claim 17, Shin discloses all of the elements of the claimed invention discussed above regarding claim 16. Shin further discloses in figure 2, wherein in the orthographic projection pattern of the array substrate, and the barrier wall is located on an outer periphery of the second line segment.
As to claim 18, Shin discloses all of the elements of the claimed invention discussed above regarding claim 17. Shin further discloses in figures 8 and 9, a barrier wall 400 located on an outside of the first line segment away from the second line segment.
As to claim 20, Shin discloses all of the elements of the claimed invention discussed above regarding claim 17. Shin further discloses in figure 2, wherein a distance between the wiring portion 151 and the third line segment 151 is greater than a distance between the connection portion 130 and the third line segment 151.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 2021/0325714).
As to claim 13, Shin discloses all of the elements of the claimed invention discussed above regarding claim 1, but does not disclose wherein a distance between the second line segment and the third line segment is greater than or equal to 20.4 microns. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shin wherein a distance between the second line segment and the third line segment is greater than or equal to 20.4 microns, in order to prevent crosstalk interference.
As to claim 14, Shin discloses all of the elements of the claimed invention discussed above regarding claim 1, but does not disclose wherein a thickness of the second insulation layer is greater than or equal to 1000 Å. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shin wherein a thickness of the second insulation layer is greater than or equal to 1000 Å, in order to provide sufficient insulation to the signal lines.
Allowable Subject Matter
Claims 4, 6-12 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art taught or fairly suggested an array substrate comprising the combination required by claim 4, wherein the array substrate comprises a gate driver circuit unit, the first signal line is a low frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driver circuit unit, and the wiring portion is connected to the gate driver circuit unit; the second signal line further comprises a fourth line segment, the fourth line segment and the first line segment are located on a same layer and are spaced from each other on the substrate, and the first insulation layer covers the fourth line segment; the fourth line segment is located on a side of the first line segment away from the gate driver circuit unit, at least one second via hole is defined in the first insulation layer, the second via hole exposes the fourth line segment, and the third line segment is connected to the fourth line segment through the second via hole; and in the orthographic projection pattern of the array substrate, the barrier wall is located between the first line segment and the fourth line segment.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art taught or fairly suggested an array substrate comprising the combination required by claim 6, wherein in the orthographic projection pattern of the array substrate, the barrier wall at least completely covers the connection portion. Claims 7-8 and 12 are objected to by virtue of their dependency.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art taught or fairly suggested an array substrate comprising the combination required by claim 9, wherein a hollow opening is defined in the first line segment, and in the orthographic projection pattern of the array substrate, at least a portion of the hollow opening is located between the second line segment and the third line segment; and the first insulation layer covers the hollow opening to form a recess, at least one region of the recess is disposed between the second line segment and the third line segment. Claims 10-11 are objected to by virtue of their dependency.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art taught or fairly suggested a display panel comprising the combination required by claim 19, wherein the array substrate comprises a gate driver circuit unit, the first signal line is a low frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driver circuit unit, and the wiring portion is connected to the gate driver circuit unit; the second signal line further comprises a fourth line segment, the fourth line segment and the first line segment are located on a same layer and are spaced from each other on the substrate, and the first insulation layer covers the fourth line segment; the fourth line segment is located on a side of the first line segment away from the gate driver circuit unit, at least one second via hole is defined in the first insulation layer, the second via hole exposes the fourth line segment, and the third line segment is connected to the fourth line segment through the second via hole; and in the orthographic projection pattern of the array substrate, the barrier wall is located between the first line segment and the fourth line segment.
Conclusion
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/DAVID Y CHUNG/Examiner, Art Unit 2871
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