DETAILED ACTION
This action is in response to the application filed on 12/16/2022. Claims 1-20 are pending and have been
examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the input system". There is insufficient antecedent basis for this limitation in the claim. Claim 3 is dependent on claim 1, which does not claim any input system. For examining purposes, the input system from claim 3 will be interpreted as the input system from claim 2. Examiner recommends amending claim 3 to be dependent on claim 2 since claim 2 does claim an input system.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 6-8, 14, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davies et al. (US 20180174032 A1) (hereafter referred to as Davies) in view of Akopyan et al. (TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip) (hereafter referred to as Akopyan).
Regarding claim 1, Davies teaches
A computer-implemented method for controlling the firing of neurons within a neuron layer of a spiking neural network (Davies, Abstract, “Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages”. Examiner notes that neuromorphic traffic control maps to a spiking neural network).
by a handshake controller associated with the neuron layer, receiving a request for firing the neurons and, in response, generating a tick signal (Davies, paragraph 0131, “Example 47 is a system for neuromorphic traffic control, the system comprising: a plurality of neuron cores organized on a chip to send and receive neuromorphic event messages; a mesh connecting the plurality of neuron cores and used to send and receive the neuromorphic event messages, the mesh including a network of routers organized as a grid with nearest-neighbor connectivity among routers of the network of routers; and a first core of the plurality of neuron cores to: send a first barrier synchronization token along the mesh to a neighbor neuron core in the plurality of neuron cores; receive a second barrier synchronization token along the mesh from the neighbor neuron core; and increment, in response to receiving the second barrier synchronization token, a time-step counter of the first core” and “the barrier synchronization specifies to a core that the core may proceed to do a “next” action. A SEQUENCER unit of a neuron core or software on a core may be configured to agree on the next action” (Akopyan, paragraph 0034). Examiner notes that the receiving neuromorphic messages maps to the request for firing the neuron, while the barrier synchronization token maps to the tick signal and the sequencer unit of the neuron core maps to the handshake controller).
upon receiving the tick signal, by the respective neurons, firing the respective neurons that fulfil a firing condition based on the neuron state (Davies, paragraph 0016, “An example neuromorphic technique works by causing each core to evaluate its neurons at a current time-step, sending zero or more spikes to other cores if its neurons fire. Before starting a next time-step, all cores should receive all the spikes intended for that time-step. After the cores finish sending spikes, they may execute a “barrier synchronization” technique to flush all spikes out of the fabric and let all the cores know when to begin the next time-step”).
Davies does not teach, but Akopyan does teach,
by the respective neurons, updating a neuron state when receiving a neuron input (Akopyan, Section V-F, page 1546, “Internally, to process each neuron, the token controller sends a token through a chain of asynchronous shift registers (267 registers) and corresponding logic blocks. In the asynchronous register array, 256 registers contain data about which neurons need to be updated”).
Davies and Akopyan are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies to update each neuron from Akopyan. Akopyan teaches “the Token controller is a key to lowering active power consumption and implementing the high-speed design required for real-time operation” (Akopyan, Section F, page 1547) (See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 6, Davies and Akopyan teach the method of claim 1, Davies further teaches
the spiking neural network comprises a sequence of connected neuron layers and a plurality of handshake controllers associated with the respective neuron layers (Davies, paragraph 0027, “A fundamental support in each core may execute a sequential state-machine where at each step, the core waits for N expected barrier tokens (where N may be 0). Then the core sends M output barrier tokens to specified cores (where M may be 0). N and M may be small numbers, such as 2, 3, or 4 bits. Each step may optionally launch the next “action” (e.g., updating or learning in the core). The leader neuron core 102 may be a lowest numbered core in a tile. Other cores, such as 108, 110, or 112 may be tile-followers. The tile-followers may run a simpler sequence than the leader neuron core 102”).
Regarding claim 7, Davies and Akopyan teach the method of claim 1, Davies further teaches
receiving the request for firing the neurons from one or more handshake controllers associated with respective preceding neuron layers (Davies, paragraph 0018, “In an example, a southeast core (e.g., a core in a bottommost and rightmost location on an arbitrary orientation of a chip) starts sending tokens both north and west (e.g. to a neighbor core upwards in the arbitrary orientation and to a neighbor core to the left in the arbitrary orientation), and then each core after that may wait for those tokens to arrive before sending tokens onward north and west” and “In Example 50, the subject matter of Example 49 optionally includes wherein the at least two neighbor neuron cores are to forward the barrier synchronization token to subsequent neighbor neuron cores of the plurality of neuron cores, and wherein the barrier synchronization token is to be forwarded by the subsequent neighbor neuron cores until the barrier synchronization token reaches a northernmost and westernmost core in the plurality of neuron cores on the chip” (Davies, paragraph 0134)).
Regarding claim 8, Davies and Akopyan teach the method of claim 1, Davies further teaches
by a handshake controller associated with a neuron layer, forwarding a request for firing the neurons to one or more handshake controllers associated with respective successive neuron layers (Davies, paragraph 0018, “In an example, a southeast core (e.g., a core in a bottommost and rightmost location on an arbitrary orientation of a chip) starts sending tokens both north and west (e.g. to a neighbor core upwards in the arbitrary orientation and to a neighbor core to the left in the arbitrary orientation), and then each core after that may wait for those tokens to arrive before sending tokens onward north and west” and “In Example 49, the subject matter of Example 48 optionally includes wherein the first barrier synchronization token is sent to at least two neighbor neuron cores, one of the at least two neighbor neuron cores located one core north of the first core and another of the at least two neighbor neuron cores located one core west of the first core, and wherein the first barrier synchronization token is sent north to the one and west to the another of the at least two neighbor neuron cores” (Davies, paragraph 0133)).
Regarding claim 14, Davies teaches
A processor configured to perform the computer implemented method (Davies, paragraph 0083, “Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described above. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products”).
by a handshake controller associated with the neuron layer, receiving a request for firing the neurons and, in response, generating a tick signal (Davies, paragraph 0131, “Example 47 is a system for neuromorphic traffic control, the system comprising: a plurality of neuron cores organized on a chip to send and receive neuromorphic event messages; a mesh connecting the plurality of neuron cores and used to send and receive the neuromorphic event messages, the mesh including a network of routers organized as a grid with nearest-neighbor connectivity among routers of the network of routers; and a first core of the plurality of neuron cores to: send a first barrier synchronization token along the mesh to a neighbor neuron core in the plurality of neuron cores; receive a second barrier synchronization token along the mesh from the neighbor neuron core; and increment, in response to receiving the second barrier synchronization token, a time-step counter of the first core” and “the barrier synchronization specifies to a core that the core may proceed to do a “next” action. A SEQUENCER unit of a neuron core or software on a core may be configured to agree on the next action” (Akopyan, paragraph 0034). Examiner notes that the receiving neuromorphic messages maps to the request for firing the neuron, while the barrier synchronization token maps to the tick signal and the sequencer unit of the neuron core maps to the handshake controller).
upon receiving the tick signal, by the respective neurons, firing the respective neurons that fulfil a firing condition based on the neuron state (Davies, paragraph 0016, “An example neuromorphic technique works by causing each core to evaluate its neurons at a current time-step, sending zero or more spikes to other cores if its neurons fire. Before starting a next time-step, all cores should receive all the spikes intended for that time-step. After the cores finish sending spikes, they may execute a “barrier synchronization” technique to flush all spikes out of the fabric and let all the cores know when to begin the next time-step”).
Davies does not teach, but Akopyan does teach,
by the respective neurons, updating a neuron state when receiving a neuron input (Akopyan, Section V-F, page 1546, “Internally, to process each neuron, the token controller sends a token through a chain of asynchronous shift registers (267 registers) and corresponding logic blocks. In the asynchronous register array, 256 registers contain data about which neurons need to be updated”).
Davies and Akopyan are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies to update each neuron from Akopyan. Akopyan teaches “the Token controller is a key to lowering active power consumption and implementing the high-speed design required for real-time operation” (Akopyan, Section F, page 1547) (See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 15, Davies teaches
A computer-readable medium comprising stored non-transitory instructions executable by a computer (Davies, paragraph 0083, “Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMS), read only memories (ROMs), and the like”).
by a handshake controller associated with the neuron layer, receiving a request for firing the neurons and, in response, generating a tick signal (Davies, paragraph 0131, “Example 47 is a system for neuromorphic traffic control, the system comprising: a plurality of neuron cores organized on a chip to send and receive neuromorphic event messages; a mesh connecting the plurality of neuron cores and used to send and receive the neuromorphic event messages, the mesh including a network of routers organized as a grid with nearest-neighbor connectivity among routers of the network of routers; and a first core of the plurality of neuron cores to: send a first barrier synchronization token along the mesh to a neighbor neuron core in the plurality of neuron cores; receive a second barrier synchronization token along the mesh from the neighbor neuron core; and increment, in response to receiving the second barrier synchronization token, a time-step counter of the first core” and “the barrier synchronization specifies to a core that the core may proceed to do a “next” action. A SEQUENCER unit of a neuron core or software on a core may be configured to agree on the next action” (Akopyan, paragraph 0034). Examiner notes that the receiving neuromorphic messages maps to the request for firing the neuron, while the barrier synchronization token maps to the tick signal and the sequencer unit of the neuron core maps to the handshake controller).
upon receiving the tick signal, by the respective neurons, firing the respective neurons that fulfil a firing condition based on the neuron state (Davies, paragraph 0016, “An example neuromorphic technique works by causing each core to evaluate its neurons at a current time-step, sending zero or more spikes to other cores if its neurons fire. Before starting a next time-step, all cores should receive all the spikes intended for that time-step. After the cores finish sending spikes, they may execute a “barrier synchronization” technique to flush all spikes out of the fabric and let all the cores know when to begin the next time-step”).
Davies does not teach, but Akopyan does teach,
by the respective neurons, updating a neuron state when receiving a neuron input (Akopyan, Section V-F, page 1546, “Internally, to process each neuron, the token controller sends a token through a chain of asynchronous shift registers (267 registers) and corresponding logic blocks. In the asynchronous register array, 256 registers contain data about which neurons need to be updated”).
Davies and Akopyan are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies to update each neuron from Akopyan. Akopyan teaches “the Token controller is a key to lowering active power consumption and implementing the high-speed design required for real-time operation” (Akopyan, Section F, page 1547) (See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 20, Davies and Akopyan teach the computer-readable medium comprising stored non-transitory instructions of claim 15, Davies further teaches
the spiking neural network comprises a sequence of connected neuron layers and a plurality of handshake controllers associated with the respective neuron layers (Davies, paragraph 0027, “A fundamental support in each core may execute a sequential state-machine where at each step, the core waits for N expected barrier tokens (where N may be 0). Then the core sends M output barrier tokens to specified cores (where M may be 0). N and M may be small numbers, such as 2, 3, or 4 bits. Each step may optionally launch the next “action” (e.g., updating or learning in the core). The leader neuron core 102 may be a lowest numbered core in a tile. Other cores, such as 108, 110, or 112 may be tile-followers. The tile-followers may run a simpler sequence than the leader neuron core 102”).
Claim(s) 2-3, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Akopyan and Boahen et al. (Point-to-Point Connectivity Between Neuromorphic Chips) (here after referred to as Boahen).
Regarding claim 2, Davies and Akopyan teach the method of claim 1, Davies and Akopyan do not teach, but Boahen does teach
by the handshake controller, receiving the request for firing the neurons from an input system that is coupled to an input layer of the spiking neural network (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays… The 2-D AER receiver’s structure parallels that of the transmitter, as shown in Fig. 12. First, we use a-bit decoder to select one of the rows, and then we use a-bit decoder to select one of the output ports assigned to that row. This strategy is realized by the circuit shown in Fig. 14, obtained by decomposing AERCV (N) into neuron, row, and column subprocesses, and following the synthesis procedure. The gate that combines the row- and column-selects is changed from a state-holding C-element to a purely combinational NAND gate”).
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Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Regarding claim 3, Davies and Akopyan teach the method of claim 1, Davies and Akopyan do not teach, but Boahen does teach
by the respective neurons, receiving the neuron input from the input system (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays… The 2-D AER receiver’s structure parallels that of the transmitter, as shown in Fig. 12. First, we use a-bit decoder to select one of the rows, and then we use a-bit decoder to select one of the output ports assigned to that row. This strategy is realized by the circuit shown in Fig. 14, obtained by decomposing AERCV (N) into neuron, row, and column subprocesses, and following the synthesis procedure. The gate that combines the row- and column-selects is changed from a state-holding C-element to a purely combinational NAND gate”).
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Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Regarding claim 16, Davies and Akopyan teach the computer-readable medium comprising stored non-transitory instructions of claim 15, Davies and Akopyan do not teach, but Boahen does teach
receive, by the handshake controller, the request for firing the neurons from an input system that is coupled to an input layer of the spiking neural network (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays… The 2-D AER receiver’s structure parallels that of the transmitter, as shown in Fig. 12. First, we use a-bit decoder to select one of the rows, and then we use a-bit decoder to select one of the output ports assigned to that row. This strategy is realized by the circuit shown in Fig. 14, obtained by decomposing AERCV (N) into neuron, row, and column subprocesses, and following the synthesis procedure. The gate that combines the row- and column-selects is changed from a state-holding C-element to a purely combinational NAND gate”).
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Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Regarding claim 17, Davies and Akopyan teach the computer-readable medium comprising stored non-transitory instructions of claim 15, Davies and Akopyan do not teach, but Boahen does teach
receive, by the respective neurons, the neuron input from the input system (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays… The 2-D AER receiver’s structure parallels that of the transmitter, as shown in Fig. 12. First, we use a-bit decoder to select one of the rows, and then we use a-bit decoder to select one of the output ports assigned to that row. This strategy is realized by the circuit shown in Fig. 14, obtained by decomposing AERCV (N) into neuron, row, and column subprocesses, and following the synthesis procedure. The gate that combines the row- and column-selects is changed from a state-holding C-element to a purely combinational NAND gate”).
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Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Claim(s) 4-5, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Akopyan, Boahen, and Amir et al. (Cognitive Computing Programming Paradigm: A Corelet Language for Composing Networks of Neurosynaptic Cores) (hereafter referred to as Amir).
Regarding claim 4, Davies and Akopyan teach the method of claim 1, Davies and Akopyan do not teach, but Boahen does teach
by the handshake controller, transmitting a request for accepting an output of the spiking neural network to an output system that is coupled to an output layer of the spiking neural network (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays. 1) 2-D Transmitter: Neurons in a 2-D AER transmitter are selected by performing hierarchical row-first column-second arbitration, as shown in Fig. 12. First, we use a-input arbiter to choose one of rows, and then we use a-input arbiter to choose one of neurons assigned to that row. Hence, we can share a single-input column-arbiter between all the rows. We must OR together all requests within each row to generate requests for the row arbiter, and all requests within each column to generate requests for the column arbiter”).
Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Davies, Akopyan, and Boahen do not teach, but Amir does teach
by the handshake controller, transmitting a request for accepting an output of the spiking neural network to an output system that is coupled to an output layer of the spiking neural network (Amir, Section C. Contributions, “a new programming paradigm that consists of (a) a corelet, namely an abstraction that represents a TrueNorth program that only exposes external inputs and outputs while encapsulating all other details of the network of neurosynaptic cores…A corelet (Fig. 2) is an abstraction of a network of neurosynaptic cores that encapsulates all intra-network connectivity and all intra-core physiology and only exposes external inputs to and external outputs from the network. We group inputs and outputs into connectors. A corelet user has access only to input and output connectors”. Examiner notes that the outlet connector maps to the output layer)
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Davies, Akopyan, Boahen, and Amir are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies, Akopyan, and Boahen to use the corelet core from Amir. Amir teaches “an entirely new programming paradigm that can permit construction of complex cognitive algorithms and applications while being efficient for TrueNorth and effective for programmer productivity” (Amir, Section B. Motivation)(See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 5, Davies, Akopyan, Boahen, and Amir teach the method of claim 4, Davies and Akopyan do not teach, but Boahen does teach
by the handshake controller, delaying the generating of the tick signal until receiving an acknowledgment from the output system, wherein the acknowledgement is indicative for a consent to receive the output of the spiking neural network (Boahen, Section IV-C, “The neuron drives the row-request line low (i.e., p-) when a spike occurs (lix). The controller relays this request to the row arbiter (ro+) and grants the request by driving the row-select line high (s+) when the arbiter acknowledges (ri). It also activates the row-address–encoder (ao+). If necessary, the controller waits until previous column and encoder communications are completed (ai). When the row is selected, all neurons with spikes place requests on their column lines (cox-) and clear their spikes one by one, by taking lox low, as these requests are granted (cix)”).
Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Regarding claim 18, Davies and Akopyan teach the computer-readable medium comprising stored non-transitory instructions of claim 15, Davies and Akopyan do not teach, but Boahen does teach
by the handshake controller, transmitting a request for accepting an output of the spiking neural network to an output system that is coupled to an output layer of the spiking neural network (Boahen, Section IV-C, “Both sending and receiving neural populations may be organized into 2-D arrays. 1) 2-D Transmitter: Neurons in a 2-D AER transmitter are selected by performing hierarchical row-first column-second arbitration, as shown in Fig. 12. First, we use a-input arbiter to choose one of rows, and then we use a-input arbiter to choose one of neurons assigned to that row. Hence, we can share a single-input column-arbiter between all the rows. We must OR together all requests within each row to generate requests for the row arbiter, and all requests within each column to generate requests for the column arbiter”).
Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Davies, Akopyan, and Boahen do not teach, but Amir does teach
by the handshake controller, transmitting a request for accepting an output of the spiking neural network to an output system that is coupled to an output layer of the spiking neural network (Amir, Section C. Contributions, “a new programming paradigm that consists of (a) a corelet, namely an abstraction that represents a TrueNorth program that only exposes external inputs and outputs while encapsulating all other details of the network of neurosynaptic cores…A corelet (Fig. 2) is an abstraction of a network of neurosynaptic cores that encapsulates all intra-network connectivity and all intra-core physiology and only exposes external inputs to and external outputs from the network. We group inputs and outputs into connectors. A corelet user has access only to input and output connectors”. Examiner notes that the outlet connector maps to the output layer)
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Davies, Akopyan, Boahen, and Amir are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies, Akopyan, and Boahen to use the corelet core from Amir. Amir teaches “an entirely new programming paradigm that can permit construction of complex cognitive algorithms and applications while being efficient for TrueNorth and effective for programmer productivity” (Amir, Section B. Motivation)(See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 19, Davies and Akopyan teach the computer-readable medium comprising stored non-transitory instructions of claim 15, Davies and Akopyan do not teach, but Boahen does teach
delay, by the handshake controller, the generating of the tick signal until receiving an acknowledgment from the output system, wherein the acknowledgement is indicative for a consent to receive the output of the spiking neural network (Boahen, Section IV-C, “The neuron drives the row-request line low (i.e., p-) when a spike occurs (lix). The controller relays this request to the row arbiter (ro+) and grants the request by driving the row-select line high (s+) when the arbiter acknowledges (ri). It also activates the row-address–encoder (ao+). If necessary, the controller waits until previous column and encoder communications are completed (ai). When the row is selected, all neurons with spikes place requests on their column lines (cox-) and clear their spikes one by one, by taking lox low, as these requests are granted (cix)”).
Davies, Akopyan, and Boahen are considered analogous to the claimed invention because they deal with neuromorphic systems. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to have their neurons send and receive requests from Boahen. One of the ordinary skill in the art would have known to apply the known technique of neurons communicating with each other in a neuromorphic system. Therefore, applying Boahen’s technique would yield the predicable result of a higher performance and more energy efficient model (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Akopyan and Merolla et al. (A Multicast Tree Router for Multichip Neuromorphic Systems)
Regarding claim 9, Davies, Akopyan and Boahen teach the method of claim 6, Davies, Akopyan, and Boahen do not teach, but Merolla does teach
the spiking neural network is a recurrent spiking neural network, the spiking neural network comprises a multi-layer to single-layer connection, the spiking neural network comprises a single- layer to multi-layer connection, and/or the spiking neural network comprises a multi- layer to multi-layer connection (Merolla, Section V-A, “To test the router’s multicast capability, and thereby demonstrate our central claim of deadlock-free, multicast routing, we configured Neurogram to simulate a neural network with fifteen cell-layers. The layers were arranged in a ring—the first and last were neighbors—each layer connected to its three nearest neighbors on either side”. Examiner notes that this maps to a multi-layer to multi-layer recurrent connection).
Davies, Akopyan, Boahen, and Merolla are considered analogous to the claimed invention because they deal with neuromorphic system. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies, Akopyan, and Boahen to use the tree router from Merolla. Merolla teaches “Our tree router implements this one-to-many routing by branching recursively—broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree’s root” (Merolla, Abstract) (See MPEP 2141 (III)(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention).
Regarding claim 10, Davies, Akopyan, Boahen, and Merolla teach the method of claim 9, Davies further teaches
receiving the request for firing the neurons from one or more handshake controllers associated with respective preceding neuron layers (Davies, paragraph 0018, “In an example, a southeast core (e.g., a core in a bottommost and rightmost location on an arbitrary orientation of a chip) starts sending tokens both north and west (e.g. to a neighbor core upwards in the arbitrary orientation and to a neighbor core to the left in the arbitrary orientation), and then each core after that may wait for those tokens to arrive before sending tokens onward north and west” and “In Example 50, the subject matter of Example 49 optionally includes wherein the at least two neighbor neuron cores are to forward the barrier synchronization token to subsequent neighbor neuron cores of the plurality of neuron cores, and wherein the barrier synchronization token is to be forwarded by the subsequent neighbor neuron cores until the barrier synchronization token reaches a northernmost and westernmost core in the plurality of neuron cores on the chip” (Davies, paragraph 0134)).
Regarding claim 11, Davies, Akopyan, Boahen, and Merolla teach the method of claim 9, Davies further teaches
by a handshake controller associated with a neuron layer, forwarding a request for firing the neurons to one or more handshake controllers associated with respective successive neuron layers (Davies, paragraph 0018, “In an example, a southeast core (e.g., a core in a bottommost and rightmost location on an arbitrary orientation of a chip) starts sending tokens both north and west (e.g. to a neighbor core upwards in the arbitrary orientation and to a neighbor core to the left in the arbitrary orientation), and then each core after that may wait for those tokens to arrive before sending tokens onward north and west” and “In Example 49, the subject matter of Example 48 optionally includes wherein the first barrier synchronization token is sent to at least two neighbor neuron cores, one of the at least two neighbor neuron cores located one core north of the first core and another of the at least two neighbor neuron cores located one core west of the first core, and wherein the first barrier synchronization token is sent north to the one and west to the another of the at least two neighbor neuron cores” (Davies, paragraph 0133)).
Regarding claim 12, Davies, Akopyan, Boahen, and Merolla teach the method of claim 9, Davies further teaches
by the handshake controller, delaying the generating of the tick signal until receiving an acknowledgment from the one or more handshake controllers associated with the respective successive neuron layers, wherein the acknowledgement is indicative for the neurons within the respective successive neuron layers being available to evaluate the firing condition (Davies, paragraph 0131, “Example 47 is a system for neuromorphic traffic control, the system comprising: a plurality of neuron cores organized on a chip to send and receive neuromorphic event messages; a mesh connecting the plurality of neuron cores and used to send and receive the neuromorphic event messages, the mesh including a network of routers organized as a grid with nearest-neighbor connectivity among routers of the network of routers; and a first core of the plurality of neuron cores to: send a first barrier synchronization token along the mesh to a neighbor neuron core in the plurality of neuron cores; receive a second barrier synchronization token along the mesh from the neighbor neuron core; and increment, in response to receiving the second barrier synchronization token, a time-step counter of the first core.” Examiner notes the first core is gated until the second barrier synchronization token is received).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davies in view of Akopyan and Qiao et al. (Scaling Mixed-Signal Neuromorphic Processors to 28nm FD-SOI Technologies) (hereafter referred to as Qiao).
Regarding claim 13, Davies and Akopyan teach the method of claim 1, Davies teaches
delaying the generating of the tick signal until receiving an additional signal from one or more neurons within the neuron layer associated with the handshake controller, wherein the additional signal is indicative for a respective neuron within the neuron layer being available to fire (Davies, paragraph 0131, “Example 47 is a system for neuromorphic traffic control, the system comprising: a plurality of neuron cores organized on a chip to send and receive neuromorphic event messages; a mesh connecting the plurality of neuron cores and used to send and receive the neuromorphic event messages, the mesh including a network of routers organized as a grid with nearest-neighbor connectivity among routers of the network of routers; and a first core of the plurality of neuron cores to: send a first barrier synchronization token along the mesh to a neighbor neuron core in the plurality of neuron cores; receive a second barrier synchronization token along the mesh from the neighbor neuron core; and increment, in response to receiving the second barrier synchronization token, a time-step counter of the first core.” Examiner notes the first core is gated until the second barrier synchronization token is received).
Davies does not teach, but Qiao does teach
delaying the generating of the tick signal until receiving an additional signal from one or more neurons within the neuron layer associated with the handshake controller, wherein the additional signal is indicative for a respective neuron within the neuron layer being available to fire (Qiao, Section II-B, “The process stage includes Handshaking, Validity and Buffer blocks. With dual-rail data protocol, the request signal from a previous stage is encoded in data, the Validity module checks the validity of input data and identifies the state via the signal in.v. The handshaking block generates the acknowledge signal in.a to acknowledge its previous stage for valid input”)
Davies, Akopyan, and Qiao are considered analogous to the claimed invention because they deal with neuromorphic system. It would have been obvious to one having ordinary skill in the art prior to the effective filling date to modified Davies and Akopyan to use the validity module from Qiao. One of the ordinary skill in the art would have known to apply the known technique of sending the state of neurons to each other. Therefore, applying Qiao’s technique would yield the predicable result of ensuring network stability and allows neurons to process more efficiently (See MPEP 2141 (III)(D) Applying a known technique to a known device ready for improvement to yield predicable results).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chundi et al. (Always-On Sub-Microwatt Spiking Neural Network Based on Spike-Driven Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device) discloses a SNN classifier architecture that employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. Rivera et al. (US 10839287 B1) discloses a globally asynchronous and locally synchronous neuromorphic network.
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/S.V./ Examiner, Art Unit 2148 /MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148
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