DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office correspondence.
Drawings
The Drawings filed on 12/15/2023, have been acknowledged.
Priority
Acknowledgment is made of applicant’s claim for a foreign priority under 35 U.S.C. 119 from United Kingdom patent application No. GB2218962.5 filed on 15 December 2022.
Information Disclosure Statement
The information disclosure statement IDS(s) submitted on 12/15/2023 and 02/22/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Content of Specification
The title of the invention, “Hardware Mapping”, is not fully descriptive of the invention. The instant application describes a method for mapping program to hardware arrangement that involves generation of non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages. Hence, the Examiner requests a new title that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C 101 because the claimed invention is directed to abstract idea without significantly more.
Step 1:
The claims are directed to a process and a system, wherein the claimed process describes mapping of a program to a hardware arrangement comprising a plurality of interconnected hardware stages; wherein the hardware stages in the hardware arrangement are analyzed to generate, for each stage, a program-independent hardware description defining an operation performed by the stage that includes inputs and outputs of the stage. The program-independent hardware descriptions are then used when analyzing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement. Then, these groups of adjacent program primitive operations are scheduled into an order for execution.
Step 2A – Prong One – The claims recite an abstract idea
Independent claims 1 and 18 are directed to an abstract idea without significantly more.
The claim(s) recites the following limitation: “analysing the plurality of hardware stages in the hardware arrangement to generate, for each stage, a program-independent hardware description defining an operation performed by the stage and inputs and outputs of the stage.” The aforementioned claim language recites process steps that, under its broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting: “a computing-based device”, “a processor” and/or “a memory”, nothing in the claim element precludes the steps from practically being performed in a human mind. For example, and given some information at hand of hardware stages that are recited at a high-level, a person is mentally capable, or with the aid of pen and paper, of analyzing this information at hand and able to produce/generate description (as claimed) of these hardware components/stages, which is a mental process.
The aforementioned claim continues to recite the following – “analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement based on the program independent hardware descriptions.” At this step, the cited language of: “analysing the program to generate a non-overlapping set of mappings between groups of … based on the … descriptions”, which include a series of steps that recite a mental process of comparing information, i.e. program primitive operations, against some other set of information, i.e. hardware description, which under its broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting “a computing-based device”, “a processor” and/or “a memory”, nothing in the claim element precludes the steps from practically being performed by a person, or with the aid of pen and paper, to analyze information/description and evaluate comparisons as explained above, which are steps grouped under abstract idea of a mental process.
Additionally, the aforementioned claim continues to recite the following – “scheduling the groups of adjacent program primitive operations into an order for execution”, which include a series of steps that recite a mental process of analyzing information at hand and create an ordered list of actions, which under its broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting “a computing-based device”, “a processor” and/or “a memory”, nothing in the claim element precludes the steps from practically being performed by a person, or with the aid of pen and paper, analyzing information at hand and create an ordered list of actions, which are steps grouped under abstract idea of a mental process.
As explained above, a process of “analysing the plurality of hardware stages, …”, “analysing the program to generate a non-overlapping …”, and “scheduling the groups … into an order for execution”, recite nothing more than an abstract idea. Consequently, if a claim limitation, under its broadest reasonable interpretation, covers an abstract idea that includes a series of steps that recite mental steps, but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of “Abstract Ideas”. Accordingly, the aforementioned claim(s) recite abstract ideas.
Step 2A – Prong Two - The abstract idea is not integrated into a practical application
This judicial exception is not integrated into a practical application. Furthermore, the aforementioned claim limitations do not seem to recite any additional claim limitations for consideration at this step of claim analysis.
The additional elements recited in the aforementioned claim(s) are: “computing-based device”, “processor” and “memory”. The additional elements of using a computer, storage device(s) and processor(s) to obtain information, analyze information, and manipulate information amounts to no more than mere instructions to apply the judicial exception using generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. See MPEP 2106.05(f).
Step 2B:
The claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additionally, the “computing-based device”, “processor” and “memory” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component that are well-known and conventional and cannot provide an inventive concept.
Thus, there are no additional elements that amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that any combination of elements improves the functioning of a computer or improves any other technology.
The claim(s) is not patent eligible.
Claim 2 is dependent on claim 1 and includes all the limitations of claim 1. Further, the aforementioned claim recites the additional limitations of “for each program primitive operation in the program, using the program independent hardware descriptions to generate one or more mappings between the program primitive operation and different compatible hardware stages in the hardware arrangement.” At this step, the recited language of “using the program independent hardware descriptions to generate one or more mappings …”, which continues to recite a mental process of comparing information, i.e. program primitive operations, against some other set of information, i.e. hardware description, which under its broadest reasonable interpretation covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
The aforementioned claim continues to recite the following limitations: “generating a plurality of candidate group mappings, wherein each candidate group mapping maps a group of adjacent program primitive operations in the program to a group of interconnected hardware stages, by analysing inputs and outputs of the program primitive operations and hardware stages.” At this step, the recited language of “generating a plurality of candidate group mappings, …, by analysing inputs and outputs of the program primitive operations and hardware stages”, again continues to recite a mental process of comparing/analyzing information, i.e. program primitive operations, against some other set of information to generate some group mappings, which under its broadest reasonable interpretation covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
Further, the aforementioned claim continues to recite the following limitations: “filtering the plurality of candidate group mappings to generate a non-overlapping set of mappings.” At this step, the recited language of “filtering … to generate a non-overlapping set of mappings”, continues to recite a mental process of comparing/analyzing information at hand to yet generate/produce a result, which is an activity that covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
Claim 3 is dependent on claim 2 and includes all the limitations of claim 2. The aforementioned claim recites the additional limitations of “using the program-independent hardware descriptions to generate all possible mappings between the program primitive operation and different compatible hardware stages in the hardware arrangement.” At this step, the recited language of “using the program-independent hardware descriptions to generate all possible mappings …”, which again continues to recite a mental process of comparing information at a high level of generality to produce an output of information comparision, i.e. “hardware descriptions to generate all possible mappings”, which under its broadest reasonable interpretation covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
Claim 4 is dependent on claim 2 and includes all the limitations of claim 2. The aforementioned claim recites the additional limitations of “wherein generating a plurality of candidate group mappings comprises excluding group mappings for any circularly dependent group of adjacent program primitive operations.” The claimed language of “…, excluding group mappings for any circularly dependent group, …”, again recite a mere mental step to compare information at hand and determine to remove/exclude some of this information, which does not amount to significantly more than the abstract idea.
Claim 5 is dependent on claim 4 and includes all the limitations of claim 4. Further, the aforementioned claim recites the additional limitation of “assigning an identifier to each primitive operation in the input program”, which this step involves a mental process to evaluate an activity and assign a label/tag/identifier to this activity, which does not amount to significantly more than the abstract idea.
The aforementioned claim continues to recite the following limitations: “for each operation, creating one or more bit vectors that encode information about each primitive operation linked to the operation through an input or output.” At this step, the recited language of “creating one or more bit vectors that encode information about each primitive operation …”, which again continues to recite a mental process of analyzing information, i.e. program primitive operations, and given some information at hand and by way of performing a mathematical mental process, a person is mentally capable, or with the aid of pen and paper, of analyzing this information at hand and be able to produce/generate an output (i.e. bit vector, which does not amount to significantly more than the abstract idea.
Further, the aforementioned claim continues to recite the following limitations: “for each group mapping, creating one or more producer bit vectors that identify primitive operations that provide inputs to the group and one or more consumer bit vectors that identify primitive operations that receive outputs from the group.” Furthermore, at this step, the recited language of “creating one or more producer bit vectors that identify primitive operations …”, continues to recite a mental process of identifying information at hand to yet generate/produce a result, which is an activity that covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
Finally, the aforementioned claim continues to recite the following limitations: “excluding group mappings where there is an overlap between producer and consumer bit vectors.” Furthermore, at this step, the recited language of “creating one or more producer bit vectors that identify primitive operations …”, continues to recite a mental process of identifying information at hand to yet generate/produce a result, which does not amount to significantly more than the abstract idea.
Claim 6 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitations of “wherein a program-independent hardware description for a hardware stage defines a number of inputs received by the hardware stage and/or a number of outputs generated by the hardware stage.” Again, at this step, the claim recited language of – “a program-independent hardware description for a hardware stage defines a number of inputs received by the hardware …”, which disclose steps to analyze information at hand and assign/define this information, which does not amount to significantly more than the abstract idea.
Claim 7 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitations of “wherein a program-independent hardware description for a hardware stage defines all inputs received by the hardware stage and/or all outputs generated by the hardware stage”, which again disclose steps to analyze information at hand and assign/define this information, which does not amount to significantly more than the abstract idea.
Claim 8 is dependent on claim 6 and includes all the limitations of claim 6. The aforementioned claim recites the additional limitation of “t wherein the program-independent hardware description for a stage defines a data format of each input and/or output”, which further disclose steps to analyze information at hand and assign/define this information, which does not amount to significantly more than the abstract idea.
Claim 9 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitation of “wherein a program-independent hardware description for a hardware stage comprises a hierarchy of a pipeline description, one or more stage descriptions, one or more operation descriptions and a plurality of input/output masks, wherein the plurality of input/output masks are nested within the one or more operation descriptions, the one or more operation descriptions are nested within the one or more stage descriptions and the one or more stage descriptions are nested within the pipeline description.” The claim recited language of “comprises a hierarchy of a pipeline description, one or more stage descriptions, one or more operation descriptions and a plurality of input/output masks, wherein the plurality of input/output masks are nested within the one or more operation descriptions, …” merely discloses mental process of evaluating description of information at hand, which does not amount to significantly more than the abstract idea.
Claim 10 is dependent on claim 9 and includes all the limitations of claim 9. The aforementioned claim recites the additional limitation of “wherein generating a plurality of candidate group mappings comprises excluding group mappings that violate a hardware stage usage constraint defined in a stage description.” The claimed language of “…, excluding group mappings …”, again recites a mere mental step to compare information at hand and determine to remove/exclude some of this information, which does not amount to significantly more than the abstract idea.
Claim 11 is dependent on claim 9 and includes all the limitations of claim 9. The aforementioned claim recites the additional limitation of “wherein filtering the plurality of candidate group mappings to generate a non-overlapping set of mappings comprises filtering the plurality of candidate group mappings according to one or more pre-defined heuristics and using data defined in the pipeline description.” The claimed language of “filtering the plurality of candidate group mappings according to one or more pre-defined heuristics …”, again recites a mere mental step to compare information at hand and determine to remove/exclude some of this information, which does not amount to significantly more than the abstract idea.
Claim 12 is dependent on claim 9 and includes all the limitations of claim 9. The aforementioned claim recites the additional limitation of “wherein an operation description comprises a plurality of input/output masks, the plurality of masks comprising a separate input mask corresponding to each possible way that data is routed to the operation and a separate output mask corresponding to each possible way that data is routed from an operation.” The claimed language of “an operation description comprises a plurality of input/output masks, …”, which again continues to recite a mere mental step to define abstract information, which does not amount to significantly more than the abstract idea.
Claim 13 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitation of “prior to analysing the plurality of hardware stages in the hardware arrangement to generate, for each stage, a program- independent hardware description: introducing one or more dummy stages between hardware stages in the plurality of hardware stages, wherein a dummy stage comprises a dummy input stage, a dummy output stage or a dummy data duplicate stage.” The claimed language of “prior to analysing the plurality of hardware stages in the hardware arrangement to generate, for each stage, a program- independent hardware description: introducing one or more dummy stages, …”, which further elaborate on the mental process of evaluating information at hand, i.e. the hardware description, then to determine of further inserting another set of detail comprising a null definition/dummy stage, which again continues to recite a mere mental step to define abstract information, which does not amount to significantly more than the abstract idea.
Claim 14 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitation of “prior to analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement: splitting a program operation in the program into a plurality of program primitive operations that collectively perform the first operation; and/or combining two or more program operations in the program into a program primitive operation that performs the combination of the two or more program operations.”
The claimed language of “prior to analysing the program to generate a non-overlapping set of mappings between groups, …, : splitting a program operation in the program into a plurality of program primitive …, and/or combining two or more program operations in the program into a program primitive …”, which further elaborate on the mental process of evaluating information at hand, i.e. the hardware description, then to determine to further “splitting a program operation in the program into a plurality of program primitive operations …” and/or to “combining two or more program, …”, which again continues to recite a mere mental step to define abstract information, which does not amount to significantly more than the abstract idea.
Claim 15 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitations of “storing the program- independent hardware descriptions for the hardware arrangement.” At this step, the claim recited language of – “storing the program- independent hardware descriptions …”, which is considered to be an insignificant extra-solution activity of mere data transmission. In this context, “storing the program- independent hardware descriptions” is an activity that is considered data manipulation activity for simply enabling a person to deal with information/data, and analyze the content of this information, which is considered to be an insignificant extra-solution activity to the judicial exception, for which an extra-solution activity includes both pre-solution and post-solution activity. In this example, the aforementioned claim limitations amount to mere data-transmission steps, and is considered insignificant extra-solution activity because it is a mere nominal or tangential addition to the claim, a mere generic process of transmission of collected and analyzed data, see MPEP 2106.05(g), which does not amount to significantly more than the abstract idea.
Claim 16 is dependent on claim 15 and includes all the limitations of claim 15.
Further, the aforementioned claim continues to recite the following limitations: “analysing the second program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the second program and groups of interconnected hardware stages in the hardware arrangement based on the stored program-independent hardware descriptions.” At this step, the recited language of “analysing the second program to generate a non-overlapping set of mappings between …”, which continues to recite a mental process of information analyzing information to produce/generate a mapping output, which does not amount to significantly more than the abstract idea.
Further, the aforementioned claim continues to recite the following limitations: “excluding group mappings where there is an overlap between producer and consumer bit vectors.” At this step, the recited language of “excluding group mappings where …”, which include a series of steps that recite a mental process of analyzing information at hand and create an ordered flow, which under its broadest reasonable interpretation covers performance of the limitation in the mind, but for the recitation of generic computer components, which does not amount to significantly more than the abstract idea.
Claim 17 is dependent on claim 1 and includes all the limitations of claim 1. The aforementioned claim recites the additional limitation of “executing the mapped groups of adjacent program primitive operations on the hardware arrangement.” At this step, the cited language of: “executing the mapped groups of adjacent program primitive …”, amounts to mere instructions to implement an abstract idea, which is a mere nominal or tangential addition to the claim which amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept, which does not amount to significantly more than the abstract idea, see MPEP 2106.05(f).
Independent claim 18 recites similar limitations to claim 1 and therefore is rejected for similar reasons as explained above.
Claim 19 is dependent on claim 18 and includes all the limitations of claim 18. The aforementioned claim recites the additional limitations of “storing the program-independent hardware descriptions for the hardware arrangement in the memory.” At this step, the claim recited language of – “storing the program-independent hardware descriptions …”, which is considered to be an insignificant extra-solution activity of mere data transmission. In this context, “storing the program- independent hardware descriptions” is an activity that is considered data manipulation activity for simply enabling a person to deal with information/data, and analyze the content of this information, which is considered to be an insignificant extra-solution activity to the judicial exception, for which an extra-solution activity includes both pre-solution and post-solution activity. In this example, the aforementioned claim limitations amount to mere data-transmission steps, and is considered insignificant extra-solution activity because it is a mere nominal or tangential addition to the claim, a mere generic process of transmission of collected and analyzed data, see MPEP 2106.05(g), which does not amount to significantly more than the abstract idea.
Claim 20 is dependent on claim 18 and includes all the limitations of claim 18. The aforementioned claim recites the additional limitations of “outputting the ordered groups of adjacent program primitive operations to the hardware arrangement for execution on the hardware arrangement.” At this step, the claim recited language of – “outputting the ordered groups of adjacent program primitive operations to the hardware …”, which is considered to be an insignificant extra-solution activity of mere data transmission. In this context, “outputting the ordered groups of adjacent program primitive operations to the hardware” is an activity that is considered data manipulation activity for simply enabling a person to deal with information/data, and analyze the content of this information, which is considered to be an insignificant extra-solution activity to the judicial exception, for which an extra-solution activity includes both pre-solution and post-solution activity. In this example, the aforementioned claim limitations amount to mere data-transmission steps, and is considered insignificant extra-solution activity because it is a mere nominal or tangential addition to the claim, a mere generic process of transmission of collected and analyzed data, see MPEP 2106.05(g), which does not amount to significantly more than the abstract idea.
The aforementioned claims are not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Publication (US 7,376,939 B1) issued to Nayak et al. (hereinafter as “NAYAK”).
Regarding claim 1, NAYAK teaches a method of mapping a program to a hardware arrangement, the hardware arrangement comprising a plurality of interconnected hardware stages (NAYAK Abstract: “Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. …; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.”; and
Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components.”,
the examiner notes that the reference discloses an automation tool that specifies:
- an architecture at a system level and its IP-cores component like embedded processors, arithmetic logic units (ALU), multipliers, divide, … (i.e. the claimed hardware stages); and
- further the reference discloses mapping the computations in an input graph produced from an application (i.e. the claimed program) to the specified target components of the architecture.
- further, the reference specifies the IP-cores and their interface; and understands IP-cores and functions via their interface including specifying component specification into an internal graph representation, which describes the capabilities and connectivity of the components and their characteristics, their interfaces and their integration within a design in the application synthesis process to the claimed language of interconnected hardware stages/components), and the method comprising:
analysing the plurality of hardware stages in the hardware arrangement to generate, for each stage, a program-independent hardware description defining an operation performed by the stage and inputs and outputs of the stage (NAYAK Col. 1, line (38): “The invention is manifested in a computer apparatus, interface specification, and/or software-implemented method for (1) specifying an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.,) (2) specifying IP-cores and their interface, (3) understanding IP-cores and functions via their interface, …”; and
Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components.”; and
Col. 2, line (18): “…, the invention provides a way to describe and specify the target architecture to the compiler in such a manner that the compiler can become independent of the target architecture, and consequently, it only needs to understand the specification of the architecture. ... This invention describes a specification language and method for describing architectures at system level and a compiler of this specification, which can make synthesis tool retargetable by following the specified process.”; and
Fig. 1, Col. 2, line (64): “FIG. 1 is an overview of an embodiment of RDL processing. Ovals in the figure describe input, output or intermediate data structures; and rectangular blocks represent processing algorithm and transformations.”; and
Col 7, line (62): “The functionality definition mechanism is a way in RDL to combine the basic operators together in a structural form to describe aggregate functionality. An already-defined functionality can also be aggregated to define new functionality. For each of the basic operators that are binary, the two inputs are referred to as left_in and right_in. The output is referred to as out.”,
the examiner notes that the reference discloses a system/method that provides a way to describe and specify the target architecture using specification language and method for describing the architectures at system level components (i.e. hardware stages) and a compiler of this specification to that of generating stage, a program-independent hardware description);
analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement based on the program-independent hardware descriptions (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching. Also, the invention may reside in specifying and processing the interface of the library functions (or IP-cores). Also, the invention may reside in identifying and processing the most suitable IP-core component to incorporate into the produced output design.”; and
Col. 3, line (20): “Constructs are provided to describe a hierarchical relationship between resources to aggregate multiple resources together to form larger resources. Along with a hierarchical relationship between resources, peer-to-peer relationships can also be specified as CONNECTIONS. A connection describes a link between two resources, via a third resource. The functionality of each resource can be extended, or new resources with new functionalities can be added.”; and
Col. 3, line (37): “Features and functionality of RDL are described herein to illustrate the use of RDL. RDL contains mechanisms to specify the structure of functions, infer the structure of components and functions specified in other languages (and therefore in a language independent manner), understand the interface and behavior of components and functions, understand the timing behavior of functions and components, and mechanisms to compile and synthesize based on the specifications.”; and
Col. 4, line (32): “In order to determine which function or operation from an application can be implemented using which resource, unique signatures are generated for both.”; and
Col. 5, line (22): “These basic operators are used to convey the functionality implemented by a specific hardware unit. In addition, these operators can be aggregated together to construct more complex functionality (illustrated later) using the FUNCTIONALITY construct.”,
the examiner notes that the reference discloses basic operators with unique signatures, i.e. non-overlapping set of mappings, are used to convey the functionality implemented by a specific hardware unit to that of the hardware operators can be aggregated together to construct more complex functionality to that of groups of interconnected hardware stages through a hierarchical relationship that matches the application graph representation of the software); and
scheduling the groups of adjacent program primitive operations into an order for execution (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching.”; and
Col. 10, line (50): “This interface facilitates the flow of information between the compiler and the architecture, which enables the Scheduling and IP Core Integration pass to realize fully the optimization features in hardware and take scheduling and allocation decisions accordingly.”,
the examiner notes that the reference discloses that in mapping the application written in high-level language onto the hardware architecture components by performing graph matching and then scheduling and allocation decisions accordingly to that of scheduling the groups of adjacent program primitive operations into an order for execution).
Regarding claim 18, the aforementioned independent claim recites similar limitations to claim 1 and therefore rejected for similar reasons as mentioned above.
Regarding claim 2, NAYAK teaches the limitations of claim 1. Further, NAYAK teaches wherein analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement based on the program-independent hardware descriptions (NAYAK Col. 1, line (38): “The invention is manifested in a computer apparatus, interface specification, and/or software-implemented method for (1) specifying an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.,) (2) specifying IP-cores and their interface, (3) understanding IP-cores and functions via their interface, …”,) comprises:
for each program primitive operation in the program, using the program-independent hardware descriptions to generate one or more mappings between the program primitive operation and different compatible hardware stages in the hardware arrangement (NAYAK Col. 1, line (57): “…, mapping the specification onto the target's components. IP cores are normally highly optimized function or computation blocks at different levels. For example, at a high-level, a library function for a filter operation (e.g., FFT) can be considered an IP block, and at a low-level structural, or register transfer level (RTL) hardware description language (HDL) on a particular platform with a well-defined interface can be considered an IP-core (or block)).”; and
Col. 4, line (32): “In order to determine which function or operation from an application can be implemented using which resource, unique signatures are generated for both. Then if the signatures match, then the resource satisfies the required functionality.”);
generating a plurality of candidate group mappings, wherein each candidate group mapping maps a group of adjacent program primitive operations in the program to a group of interconnected hardware stages, by analysing inputs and outputs of the program primitive operations and hardware stages (NAYAK Col. 5, line (40): “Newer functionality may be added to this list, which can correspond to more complex functions. The synthesis tool using the RDL to understand the IP interface and the target architecture can then infer the complex function as a basic block and automatically infer it during high-level synthesis. For example, we may define the FFT as a functionality, which the compiler can be enhanced to understand. This inference may enable the use of IP blocks performing FFTs as a basic building block, which can be inferred from system-level descriptions of an application.”; and
Fig. 1, Col. 15, line (34): “The mapping of application code (synthesis to target) entails optimally matching and mapping operators and functions to the resources so as optimally to use resources, while maximizing performance. To achieve this, one embodiment of the matching process entails graph matching as illustrated in FIG. 1. The high-level algorithm block entails the following steps: Using the construct "Create table", a table containing properties of resources and IP-cores is created. The table is populated with the characteristics of all functions and IP-cores. Earlier illustrations and FIGS. 2-4 illustrate the architecture interface and IP-core specifications. Using querying capabilities to the database containing IP-cores and resource information, which may involve complex equations, compiler is returned area, performance characteristics of a function block or an IP-core. These characteristics are used optimally to compile the application by optimized mapping onto resources.”); and
filtering the plurality of candidate group mappings to generate a non-overlapping set of mappings (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching. Also, the invention may reside in specifying and processing the interface of the library functions (or IP-cores). Also, the invention may reside in identifying and processing the most suitable IP-core component to incorporate into the produced output design.”; and
Col. 2, line (30): “Thus, as and when architectures are refined and new ones developed, a user does not have to recode the application to be synthesized onto the new target architecture, nor does the compiler need to be changed. …, suppose the current target architecture has four MAC units, which are utilized by the compiler to the fullest extent for parallelism. Now if the new target architecture has eight MAC units, the compiler can recompile the application quickly to exploit more parallelism without having to change the compiler itself.”; and
Col. 3, line (20): “Constructs are provided to describe a hierarchical relationship between resources to aggregate multiple resources together to form larger resources. Along with a hierarchical relationship between resources, peer-to-peer relationships can also be specified as CONNECTIONS. A connection describes a link between two resources, via a third resource. The functionality of each resource can be extended, or new resources with new functionalities can be added.”; and
Col. 4, line (32): “In order to determine which function or operation from an application can be implemented using which resource, unique signatures are generated for both.”,
the examiner notes that the reference discloses specifying the architecture of targets in a hierarchical manner to permit levels of refinement wherein the compiler can recompile the application quickly to exploit more parallelism without having to change the compiler itself to that of filtering the plurality of candidate group mappings to generate a non-overlapping set of mappings).
Regarding claim 3, NAYAK teaches the limitations of claim 2. Further, NAYAK teaches wherein using the program-independent hardware descriptions to generate one or more mappings between the program primitive operation and different compatible hardware stages in the hardware arrangement comprises:
using the program-independent hardware descriptions to generate all possible mappings between the program primitive operation and different compatible hardware stages in the hardware arrangement (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching. Also, the invention may reside in specifying and processing the interface of the library functions (or IP-cores). Also, the invention may reside in identifying and processing the most suitable IP-core component to incorporate into the produced output design.”; and
Col. 2, line (30): “Thus, as and when architectures are refined and new ones developed, a user does not have to recode the application to be synthesized onto the new target architecture, nor does the compiler need to be changed. As a simple example, suppose the current target architecture has four MAC units, which are utilized by the compiler to the fullest extent for parallelism. Now if the new target architecture has eight MAC units, the compiler can recompile the application quickly to exploit more parallelism without having to change the compiler itself.”; and
Col. 15, line (47): “Using querying capabilities to the database containing IP-cores and resource information, which may involve complex equations, compiler is returned area, performance characteristics of a function block or an IP-core. These characteristics are used optimally to compile the application by optimized mapping onto resources.”).
Regarding claim 6, NAYAK teaches the limitations of claim 1. Further, NAYAK teaches wherein a program-independent hardware description for a hardware stage defines a number of inputs received by the hardware stage and/or a number of outputs generated by the hardware stage (NAYAK Col. 7, line (62): “The functionality definition mechanism is a way in RDL to combine the basic operators together in a structural form to describe aggregate functionality. An already-defined functionality can also be aggregated to define new functionality. For each of the basic operators that are binary, the two inputs are referred to as left_in and right_in. The output is referred to as out. For unary operators the input is referred to as in and the output as out. A new functionality can be defined by first defining a set of input and output nodes, a set of basic operator nodes, and then specifying the connection between these nodes via the DCONNECT construct (described herein).”).
Regarding claim 7, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches wherein a program-independent hardware description for a hardware stage defines all inputs received by the hardware stage and/or all outputs generated by the hardware stage (NAYAK Fig. 1, Col. 2, line (64): “FIG. 1 is an overview of an embodiment of RDL processing. Ovals in the figure describe input, output or intermediate data structures; and rectangular blocks represent processing algorithm and transformations.”; and
Col. 7, line (62): “The functionality definition mechanism is a way in RDL to combine the basic operators together in a structural form to describe aggregate functionality. An already-defined functionality can also be aggregated to define new functionality. For each of the basic operators that are binary, the two inputs are referred to as left_in and right_in. The output is referred to as out. For unary operators the input is referred to as in and the output as out. A new functionality can be defined by first defining a set of input and output nodes, a set of basic operator nodes, and then specifying the connection between these nodes via the DCONNECT construct (described herein).”).
Regarding claim 8, NAYAK teaches the limitations of claim 6.
Further, NAYAK teaches wherein the program-independent hardware description for a stage defines a data format of each input and/or output (NAYAK Colo. 14, line (36): “The attributes to a resource are translated to functions in the resource.cpp file. …, Applications written in a high-level language are compiled into an intermediate format called Mach Intermediate format (MIF). MIF is represented in an AST. These functions take in as input a Wrapper, which contains information of the operands to the MIF AST. It has a map of the variables in the MIF AST, which are to be port mapped to the functionality graphs for the supported functionalities of a resource. It also has a list of Application Programming Interface (APIs), which are provided to the RDL writer to access all information about the variables in the MIF AST. These attribute functions return an Attribute class, which is basically a string to be interpreted by the client of the RDL compiler.”; and
Colo. 14, line (55): “A later pass flattens the functionality graph so that basic operators that are recognized from the Mach Intermediate Format (MIF) AST are present. This flattening allows a user to create functionality definition types, and use these for declaring more complex and larger functionalities in an easier manner. The functionality graph has a list of nodes, which are the input/output ports and a list of nodes, which are the internal nodes of the graph. Functions with only input/output ports qualify IP cores or basic operators.”).
Regarding claim 9, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches wherein a program-independent hardware description for a hardware stage comprises a hierarchy of a pipeline description, one or more stage descriptions, one or more operation descriptions and a plurality of input/output masks, wherein the plurality of input/output masks are nested within the one or more operation descriptions (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components.”),
the one or more operation descriptions are nested within the one or more stage descriptions and the one or more stage descriptions are nested within the pipeline description (NAYAK Col. 2, line (20): “Constructs are provided to describe a hierarchical relationship between resources to aggregate multiple resources together to form larger resources. Along with a hierarchical relationship between resources, peer-to-peer relationships can also be specified as CONNECTIONS. A connection describes a link between two resources, via a third resource. The functionality of each resource can be extended, or new resources with new functionalities can be added. The ease of defining new functionalities and the ease to aggregate them to describe new architectures provides the power and flexibility to easily retarget to a different system or specify a new system.”,
the examiner notes that the reference discloses that when a resource connection describes a link between two resources, via a third resource, to that of the one or more operation descriptions are nested).
Regarding claim 11, NAYAK teaches the limitations of claim 9. Further, NAYAK teaches wherein filtering the plurality of candidate group mappings to generate a non-overlapping set of mappings comprises filtering the plurality of candidate group mappings according to one or more pre-defined heuristics and using data defined in the pipeline description (NAYAK Fig. 5, Col. 16, line (6): “A graph-matching algorithm is then used to match parts of the AST with the dataflow graphs of the components. An example of a dataflow graph is illustrated in FIG. 5. This figure illustrates that multiple data flow graphs must be specified for the multiply and accumulate component to ensure that both the expressions (i) and (ii) are covered. This embodiment of the compiler generates all specifications to enable matching.”).
Regarding claim 12, NAYAK teaches the limitations of claim 9. Further, NAYAK teaches wherein an operation description comprises a plurality of input/output masks, the plurality of masks comprising a separate input mask corresponding to each possible way that data is routed to the operation and a separate output mask corresponding to each possible way that data is routed from an operation (NAYAK Fig. 5, Col. 16, line (1): “To specify the functionality of a component a dataflow graph corresponding to the functionality of the component is constructed. Operations in the input application are then mapped to the components in a two-step process. First the input application is parsed to construct an Abstract Syntax Tree (AST). A graph-matching algorithm is then used to match parts of the AST with the dataflow graphs of the components. An example of a dataflow graph is illustrated in FIG. 5. This figure illustrates that multiple data flow graphs must be specified for the multiply and accumulate component to ensure that both the expressions (i) and (ii) are covered. This embodiment of the compiler generates all specifications to enable matching.”).
Regarding claim 13, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches prior to analysing the plurality of hardware stages in the hardware arrangement to generate, for each stage, a program- independent hardware description: introducing one or more dummy stages between hardware stages in the plurality of hardware stages, wherein a dummy stage comprises a dummy input stage, a dummy output stage or a dummy data duplicate stage (NAYAK Col. 16, line (16): “…, the graph-matching algorithm constructs a unique signature from the dataflow graph specification of a component. It then constructs a signature for part of the AST for which a component is sought. To construct the signature a breadth first traversal of the graph is done starting from the output node as root. If more that one output node is present, a dummy node is made the parent of all output nodes. The signature is then constructed by combining recursively the signatures of intermediate nodes of the graph, starting with the leaves of the BFS tree. The signature of a node is the symbol of the node concatenated with the signatures of its children. The symbol of a leaf node is a label that denotes an input.”).
Regarding claim 14, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches prior to analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement: splitting a program operation in the program into a plurality of program primitive operations that collectively perform the first operation (NAYAK Fig. 1, Col. 2, line (64): “FIG. 1 is an overview of an embodiment of RDL processing. Ovals in the figure describe input, output or intermediate data structures; and rectangular blocks represent processing algorithm and transformations.”; and
Col. 4, line (37): “Since multiple resources can satisfy the required functionality, and a single resource can satisfy multiple functionalities, the matching process entails optimized area-performance tradeoffs to achieve optimal performance and resource usage. At the end of this process, the application is compiled onto the target.”; and
Col 7, line (62): “The functionality definition mechanism is a way in RDL to combine the basic operators together in a structural form to describe aggregate functionality. An already-defined functionality can also be aggregated to define new functionality. For each of the basic operators that are binary, the two inputs are referred to as left_in and right_in. The output is referred to as out.”; and
Table 1, Col. 4, line (43): “RDL provides basic operators shown in Table 1. The RDL compiler, whose functionality and embodiment is described later, is aware of the functionality specified by the operators in Table 1. These basic operators are an illustration of one embodiment of RDL, and may be used to demonstrate the examples and capabilities of certain aspects of this invention. The specification of these basic operators can be in any language as long as corresponding grammar is also provided for its compilation.”);
and/or combining two or more program operations in the program into a program primitive operation that performs the combination of the two or more program operations (NAYAK Table 1, Co. 5, line (22): “These basic operators are used to convey the functionality implemented by a specific hardware unit. In addition, these operators can be aggregated together to construct more complex functionality (illustrated later) using the FUNCTIONALITY construct.”).
Regarding claim 15, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches comprising storing the program-independent hardware descriptions for the hardware arrangement (NAYAL NAYAK Fig. 1, Col. 3, line (45): “The architecture of the target is presented as an input (Block 1). The design and features of the target are described using RDL (described later). RDL design is parsed and validated for syntax correctness. RDL design is then transformed into an Abstract Syntax Tree (AST), which stores the features, characteristics, interconnects of the components of the target (Block 2). The RDL may capture all current and future target architectures. Block 2 takes in as input a single RDL description of the target architecture and creates an intermediate graph representation of the architecture so as to perform optimizations. All required and important information about the target architecture to compile it can be inferred from the intermediate storage.”; and
Col. 10, line (29): “Information about the target architecture to compile it can be inferred from the intermediate storage.”).
Regarding claim 16, NAYAK teaches the limitations of claim 15.
Further, NAYAK teaches mapping a second program to the hardware arrangement (NAYAK Col. 14, line (37): “…, Applications written in a high-level language are compiled into an intermediate format called Mach Intermediate format (MIF). MIF is represented in an AST. These functions take in as input a Wrapper, which contains information of the operands to the MIF AST. It has a map of the variables in the MIF AST, which are to be port mapped to the functionality graphs for the supported functionalities of a resource. It also has a list of Application Programming Interface (APIs), which are provided to the RDL writer to access all information about the variables in the MIF AST. These attribute functions return an Attribute class, which is basically a string to be interpreted by the client of the RDL compiler.”), wherein mapping the second program to the hardware arrangement comprises:
analysing the second program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the second program and groups of interconnected hardware stages in the hardware arrangement based on the stored program-independent hardware descriptions (NAYAK Col. 1, line (38): “The invention is manifested in a computer apparatus, interface specification, and/or software-implemented method for (1) specifying an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.,) (2) specifying IP-cores and their interface, (3) understanding IP-cores and functions via their interface, …”; and
Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components.”; and
Col. 2, line (18): “…, the invention provides a way to describe and specify the target architecture to the compiler in such a manner that the compiler can become independent of the target architecture, and consequently, it only needs to understand the specification of the architecture. ... This invention describes a specification language and method for describing architectures at system level and a compiler of this specification, which can make synthesis tool retargetable by following the specified process.”; and
Fig. 1, Col. 2, line (64): “FIG. 1 is an overview of an embodiment of RDL processing. Ovals in the figure describe input, output or intermediate data structures; and rectangular blocks represent processing algorithm and transformations.”; and
Col 7, line (62): “The functionality definition mechanism is a way in RDL to combine the basic operators together in a structural form to describe aggregate functionality. An already-defined functionality can also be aggregated to define new functionality. For each of the basic operators that are binary, the two inputs are referred to as left_in and right_in. The output is referred to as out.”,
the examiner notes that the reference discloses a system/method that provides a way to describe and specify the target architecture using specification language and method for describing the architectures at system level components (i.e. hardware stages) and a compiler of this specification to that of generating stage, a program-independent hardware description); and
scheduling the groups of adjacent program primitive operations in the second program into an order for execution (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching.”; and
Col. 10, line (50): “This interface facilitates the flow of information between the compiler and the architecture, which enables the Scheduling and IP Core Integration pass to realize fully the optimization features in hardware and take scheduling and allocation decisions accordingly.”,
the examiner notes that the reference discloses that in mapping the application written in high-level language onto the hardware architecture components by performing graph matching and then scheduling and allocation decisions accordingly to that of scheduling the groups of adjacent program primitive operations into an order for execution).
Regarding claim 17, NAYAK teaches the limitations of claim 1.
Further, NAYAK teaches executing the mapped groups of adjacent program primitive operations on the hardware arrangement (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process.”;
Fig. 1, Col. 10, line (14): “The following describes the processing of RDL and its compilation. One embodiment of the RDL processing and compilation is shown in FIG. 1. The architecture of the target is presented as an input (Block 1). The design and features of the target are described using RDL (described herein). RDL design is parsed and validated for syntax correctness. RDL design is transformed into an Abstract Syntax Tree (AST), which stores the features, characteristics, and interconnects of the components of the target (Block 2). The RDL is powerful enough to capture current and future target architectures. Block 2 takes in as input a single RDL description of the target architecture and creates an intermediate graph representation of the architecture so as to perform optimizations.”; and
Col. 10, line (50): “This interface facilitates the flow of information between the compiler and the architecture, which enables the Scheduling and IP Core Integration pass to realize fully the optimization features in hardware and take scheduling and allocation decisions accordingly.”).
Regarding claim 19, NAYAK teaches the limitations of claim 18. Further, NAYAK teaches wherein the memory is further arranged to store the program-independent hardware descriptions and wherein the mapping further comprises: storing the program-independent hardware descriptions for the hardware arrangement in the memory (NAYAK Fig. 1, Col. 3, line (45): “The architecture of the target is presented as an input (Block 1). The design and features of the target are described using RDL (described later). RDL design is parsed and validated for syntax correctness. RDL design is then transformed into an Abstract Syntax Tree (AST), which stores the features, characteristics, interconnects of the components of the target (Block 2). The RDL may capture all current and future target architectures. Block 2 takes in as input a single RDL description of the target architecture and creates an intermediate graph representation of the architecture so as to perform optimizations. All required and important information about the target architecture to compile it can be inferred from the intermediate storage.”; and
Col. 10, line (29): “Information about the target architecture to compile it can be inferred from the intermediate storage.”).
Regarding claim 20, NAYAK teaches the limitations of claim 18.
Further, NAYAK teaches wherein the mapping further comprises: outputting the ordered groups of adjacent program primitive operations to the hardware arrangement for execution on the hardware arrangement (NAYAK Col. 2, line (1): “The invention may reside in specifying the architecture of targets in a hierarchical manner to permit levels of refinement. In particular, the invention may reside in specifying components and their characteristics, their interfaces and timing behavior at a high-level, and their integration within a design in the application synthesis process. Also, the invention may reside in processing the architecture and component specification into an internal graph representation, which describes the capabilities and connectivity of the components. Also, the invention may reside in mapping the application written in high-level language onto the components by performing graph matching.”; and
Col. 10, line (50): “This interface facilitates the flow of information between the compiler and the architecture, which enables the Scheduling and IP Core Integration pass to realize fully the optimization features in hardware and take scheduling and allocation decisions accordingly.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent Publication (US 7,376,939 B1) issued to Nayak et al. (hereinafter as “NAYAK”), and in view of US Patent Application Publication (US 20240201968 A1) issued to Liu et al. (hereinafter as “LIU”).
Regarding claim 4, NAYAL teaches the limitations of claim 2.
However, NAYAK does not explicitly teach wherein generating a plurality of candidate group mappings comprises excluding group mappings for any circularly dependent group of adjacent program primitive operations.
But LIU teaches wherein generating a plurality of candidate group mappings comprises excluding group mappings for any circularly dependent group of adjacent program primitive operations ( LIU Para. [0037]: “With respect to technical effects, when the third variable is a value in the updated first value interval, the second conditional statement is always true. In this case, the second conditional statement in the fifth loop statement may be eliminated, so that a quantity of instructions obtained through mapping may be reduced in a subsequent process of mapping the compilation result of the second program (multi-dimensional data obtained after partition), and instruction transmission efficiency in the mapping process is improved.”,
the examiner notes that the reference discloses a conditional loop statement may be eliminated, i.e. excluded, so that a quantity of instructions obtained through mapping, i.e. group of mappings, may be reduced in a subsequent process of mapping the compilation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NAYAK (disclosing methods for program resource specification to compile the specification onto hardware) to include the teachings of LIU (disclosing methods for program compilation and loop branch statement management) and arrive at a method to detect loop statement branches to determine removal of such statements. One of ordinary skill in the art would have been motivated to make this combination because when a compilation process in a multi-dimensional data program determines to eliminate branch jumps, thereby improving instruction transmission efficiency and further increases program mapping efficiency results, as recognized by (LIU Abstract, Para. [0006]-[0013]). In addition, the references of NAYAK and LIU teach features that are directed to analogous art and they are directed to the same field of endeavor of task scheduling and management.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent Publication (US 7,376,939 B1) issued to Nayak et al. (hereinafter as “NAYAK”), and in view of US Patent Application Publication (US 20170286169 A1) issued to Ravindran et al. (hereinafter as “RAVINDRAN”).
Regarding claim 10, NAYAK teaches the limitations of claim 9.
However, NAYAK does not explicitly teach wherein generating a plurality of candidate group mappings comprises excluding group mappings that violate a hardware stage usage constraint defined in a stage description.
But RAVINDRAN teaches generating a plurality of candidate group mappings comprises excluding group mappings that violate a hardware stage usage constraint defined in a stage description (RAVINDRAN Fig. 11/12, Para. [0116]: “FIG. 12 is a diagram illustrating an exemplary mapping of various functions of the program of FIG. 11 to various hardware elements. In this example, program functions A, B, and E are mapped to a hardware device (e.g., FPGA) in Slot 2, while functions C D and F are mapped to a device in Slot 3. Function G is mapped to a device in Slot 4, while functions H and I are mapped to a device in Slot 5. The aggregate throughput of the communications between functions E and F in the devices of Slots 2 and 3, respectively, and G in the device in Slot 4 would be 250 MB/s, which can be sustained by the PXI backplane. Similarly, the aggregate throughput of the communications between function G in the device of Slot 4 and functions H and I in the device of Slot 5, would be 1000 MB/s, which is within the bandwidth of 838 MB/s than an exemplary PXIe system can sustain. However, if function G is altered to produce 120 data tokens on each of its output channels, then the aggregate throughput of the communications between function G in the device of Slot 4 and functions H and I in the device of slot 5, would be 1000 MB/s, which is greater the bandwidth of 838 MB/s than an exemplary PXIe system can sustain. Such a mapping then would be determined to be infeasible as it violates the communication bandwidth limits of the hardware components.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of NAYAK (disclosing methods for program resource specification to compile the specification onto hardware) to include the teachings of RAVINDRAN (disclosing methods for mapping program functions to distributed heterogeneous platforms based on hardware attributes and specified constraints) and arrive at a method to exclude mappings of program functions to hardware components based on constraints. One of ordinary skill in the art would have been motivated to make this combination because when program functions are mapped for execution on hardware processing elements, wherein the mapping is based on constraint information and the attributes, however exclusion of functions mapping (i.e. pre-emptively excluding some portions of the program from some hardware elements) would be desired based on hardware constraints to ensure system reliability, as recognized by (RAVINDRAN Abstract, Para. [0006], [0050]-[0070]). In addition, the references of NAYAK and RAVINDRAN teach features that are directed to analogous art and they are directed to the same field of endeavor of resource scheduling and management.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable given the following:
If the aforementioned claims are rewritten in independent form including all of the limitations of the base claim and any intervening claims and then integrated into all independent claims; and
The applicant was able to overcome the 35 USC 101 abstract idea claims rejections of this office action.
The following is a statement of reasons for the indication of allowable subject matter. As detailed above, the combination of NAYAK and LIU teach the limitations of independent claim 1 and dependent claim 4 (which claim 5 depends from).
However, none of the above prior arts, individually or in combination, disclose that in addition the limitations of the base claim(s) and any intervening claims, that wherein excluding group mappings for any circularly dependent group of adjacent program primitive operations comprises: assigning an identifier to each primitive operation in the input program; for each operation, creating one or more bit vectors that encode information about each primitive operation linked to the operation through an input or output; for each group mapping, creating one or more producer bit vectors that identify primitive operations that provide inputs to the group and one or more consumer bit vectors that identify primitive operations that receive outputs from the group; and excluding group mappings where there is an overlap between producer and consumer bit vectors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kilgard et al.; (US-8006236-B1); “Methods for compiling high-level primitive programs into primitive program micro-code, wherein a compiler supports features if the high-level primitive program by providing conversions for different applications programming interface conventions, determining output primitive types, initializing attribute arrays based on primitive input profile modifiers, and determining vertex set lengths from specified primitive input types.”
SHAFIQ et al.; (US 20210182036 A1); “Methods for a compiler that generates one or more fused operators based on program analysis, wherein each fused operator including at least two operators of the plurality of operators which can be fused.
Aurangzeb et al.; (US 11074667 B1); “Methods for managing the improvements and optimizations of shader programs to produce optimized GPU hardware instructions, hence increasing latency for the graphics compiler.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Zuheir A Mheir whose telephone number is (571)272-4151. The examiner can normally be reached on Monday - Friday 9:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
07/23/2026
/ZUHEIR A MHEIR/Patent Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
Prosecution Insights