Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 14-19 (Group II) in the reply filed on 6/15/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/15/2024 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN113363316A) in view of Lin et al. (US20240107903A1).
Regarding Claim 14:
Zhu discloses a transistor (Fig. 4), comprising:
a stack (paragraph 21) including a gate (element 102), a gate dielectric (element 104), and a channel (element 105), wherein the channel is formed from two-dimensional (2D) layers of material (paragraph 6); and
an insert (element 103) including at least one 2D layer of material (paragraphs 5-6), the insert disposed within the gate dielectric between the gate and the channel (paragraph 21),
wherein the stack is configured to define a negative quantum capacitance (paragraph 5), such that a subthreshold slope of the transistor is less than 60 mV/dec (paragraphs 3 and 21).
However, Zhu does not explicitly disclose that the channel is formed from a plurality of two-dimensional layers.
Lin discloses an analogous stacked semiconductor device (Fig. 15, element 100d), wherein a channel (element 120) is formed from a plurality of two-dimensional (2D) layers of material (paragraphs 22 and 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Zhu further in view of Lin to explicitly include where the channel is formed from a plurality of two-dimensional layers because both are directed to analogous stacked transistor devices. Doing so improves the electrical performance of stacked transistor devices (Lin, paragraphs 22-23 and 50).
Regarding Claim 15:
The combination of Zhu and Lin disclose a transistor according to claim 14, wherein Zhu further discloses the at least one 2D layer of material of the insert (Fig. 4 element 103) is graphene, germanene, or a topological insulator (paragraph 7).
Regarding Claim 16:
The combination of Zhu and Lin disclose a transistor according to claim 14, wherein Zhu further discloses the at least one 2D layer of material of the insert is the topological insulator (Fig. 4 element 103, paragraph 5), and wherein the topological insulator is Ge, GeI, T'- WTe2, Bi2Te3, LaAlO3/SrTiO3, T'-MoTe2, or TaIrTe4 (paragraph 7).
Regarding Claim 17:
The combination of Zhu and Lin disclose a transistor according to claim 14, wherein Zhu discloses at least one layer of the plurality of 2D layers of material of the channel (Fig. 4 element 105) is: MoS2, WSe2, WTe2, or In2Se3 (paragraph 9).
Regarding Claim 18:
The combination of Zhu and Lin disclose a transistor according to claim 14, but Zhu does not explicitly disclose where the plurality of 2D channel layers include at least one layer of a first material and at least one layer of a second material, different from the first material.
Lin discloses an analogous stacked semiconductor device (Fig. 15, element 100d), wherein the plurality of 2D layers of material of the channel (element 120) includes at least one layer of a first material and at least one layer of a second, different material (paragraphs 22-24 and 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Zhu further in view of Lin to explicitly include where the plurality of two-dimensional channel layers include at least one layer of a first material and at least one layer of a – different – second material because both are directed to analogous stacked transistor devices. Doing so improves the electrical performance of stacked transistor devices (Lin, paragraphs 22-23 and 50).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (CN113363316A) in view of Lin et al. (US20240107903A1) as applied to claim 14 above, and further in view of Das et al. (US20150303315A1).
Regarding Claim 19:
The combination of Zhu and Lin disclose a transistor according to claim 14, but neither Zhu nor Lin explicitly disclose where the transistor stack is maintained under tensile strain and where the tensile strain facilitates in lowering the subthreshold slope.
However, Das discloses an analogous stacked transistor (Fig. 1C), wherein the stack (element 100) is maintained under tensile strain in a direction perpendicular to the stack (Figs. 3A-E), the tensile strain facilitating lowering the subthreshold slope (paragraphs 47-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Zhu and Lin further in view of Das to explicitly include where the transistor stack is maintained under tensile strain in a direction perpendicular to the stack. Furthermore, where said tensile strain facilitates in lowering the subthreshold slope because both are directed to analogous transistor devices. Doing so improves the electrical performance and structural integrity of transistor devices (Das, paragraphs 5-8)
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kivioja et al. (US 20130037780 A1), Xiao et al. (US 9837517 B2), Xu et al. (US 20230335589 A1), Dimitrakopoulos et al. (US 20040161873 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
Prosecution Insights