Detailed Action
The instant application having Application No. 18/541,892 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 2/13/26. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 9-12 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmi et al. (U.S. Patent Application Publication No. 2019/0278500), herein referred to as Lakshmi et al. and in view of Yang et al. (U.S. Patent Application Publication No. 2020/0005875), herein referred to as Yang et al.
Referring to claim 1, Lakshmi et al. disclose as claimed, a storage device forms a meta block based on block erase loops, the storage device comprises: a memory device including at least two dies including physical blocks for storing data (see para. 71-72, where blocks on separate dies may be grouped together to form a metablock); a controller to retrieve block data from a non-volatile memory (see fig. 2, showing both an on-die controller and a device controller), determine different categories of physical blocks on the memory device from the block data, identify an erasure marking for a physical block, form a meta block to include the physical blocks from the at least two dies, wherein the physical blocks in the meta block have a same erasure marking (see para. 72, where different blocks may be grouped together depending on their program and erase count, which would be different categories of physical blocks. The program and erase count, or PEC would be an erasure marking. Different blocks from different dies having the same PEC are grouped together into metablocks), and dynamically recategorizes and relinks the physical block to another meta block when a weight associated with the physical block exceeds an erase threshold (see para. 104, where memory elements are tracked and the controller may modify block formations based on predicted block behavior and tracked parameters. In this case, an erase threshold would be different values for the PEC).
Lakshmi et al. disclose the claimed invention except for where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell.
However, Yang et al. disclose where the erasure marking or erase threshold is erase loops or erase loop threshold (see para. 37, where erase loops are monitored and compared against an erase loop threshold); and wherein the controller confirms that the number of erase loops of the physical block has increased (see para. 37 and 51, where erase loops are monitored by the controller. See fig. 6a, 6b and 6c, showing an increase in erase loops with each erase operation), where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased (see para. 51, where the controller confirms that the number of erase loops has increased and meets a threshold) and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell (see para. 37 and 51, where if the threshold number of erase loops is met, the block may be converted from MLC type storage, which stores more bits per cell, to SLC type storage, which stores fewer bits per cell).
Lakshmi et al. and Yang et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Yang et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell., as taught by Yang al., in order to decrease wear and keep track of wear on memory (see Yang et al., para. 4-5, where keeping track of erase counts and comparing them to thresholds may lengthen the lifespan of a storage device).
As to claim 2, Lakshmi et al. and Yang et al. also disclose the storage device of claim 1, wherein during testing of the memory device, the controller performs a data mis-compare check on the physical block after completing a successful erase verify operation on the physical block, separates the physical blocks on the memory device into categories based on the data mis-compare check and stores a listing of the physical blocks with category markings in the non- volatile memory (see Lakshmi et al., para. 76-78, where during tests of the memory device, program and erase cycles are repeated to test for errors and memory elements or blocks are divided into categories based on the burn up test).
As to claim 3, Lakshmi et al. and Yang et al. also disclose the storage device of claim 2, wherein the controller places physical blocks requiring more than one erase loop in a first category and physical blocks requiring one erase loop are placed in a second category (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
As to claim 4, Lakshmi et al. and Yang et al. also disclose the storage device of claim 1, wherein a first meta block includes physical blocks from the at least two dies with one erase cycle and a second meta block includes physical blocks from the at least two dies with two erase cycles (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
As to claim 7, Lakshmi et al. and Yang et al. also disclose the storage device of claim 1, wherein in dynamically recategorizing the physical block, the controller dynamically determines that the physical block should be placed in another category associated with a different number of erase loops when a parameter associated with a physical block increases, and increases the weight assigned to the physical block (see Lakshmi et al., para. 104, where memory elements are tracked and the controller may modify block formations based on predicted block behavior and tracked parameters. In this case, an erase threshold would be different values for the PEC. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks, and therefore blocks would be recategorized into groups with different counts of erase loops depending on block parameter changes).
Referring to claim 9, Lakshmi et al. disclose as claimed, a method for forming a meta block in a storage device based on block erase loops, the storage device comprises a controller to execute the method comprising: retrieving block data for physical blocks on a memory device from a non- volatile memory (see fig. 2, showing both an on-die controller and a device controller. See para. 71-72, where blocks on separate dies may be grouped together to form a metablock); determining different categories of physical blocks on the memory device from the block data; identifying an erasure marking for a physical block from the block data; forming a meta block to include the physical blocks from the at least two dies, wherein the physical blocks in the meta block have a same erasure marking (see para. 72, where different blocks may be grouped together depending on their program and erase count, which would be different categories of physical blocks. The program and erase count, or PEC would be an erasure marking. Different blocks from different dies having the same PEC are grouped together into metablocks), and dynamically recategorizing and relinking the physical block to another meta block when a weight associated with the physical block exceeds an erase threshold (see para. 104, where memory elements are tracked and the controller may modify block formations based on predicted block behavior and tracked parameters. In this case, an erase threshold would be different values for the PEC).
Lakshmi et al. disclose the claimed invention except for where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell.
However, Yang et al. disclose where the erasure marking or erase threshold is erase loops or erase loop threshold (see para. 37, where erase loops are monitored and compared against an erase loop threshold); and wherein the controller confirms that the number of erase loops of the physical block has increased (see para. 37 and 51, where erase loops are monitored by the controller. See fig. 6a, 6b and 6c, showing an increase in erase loops with each erase operation), where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased (see para. 51, where the controller confirms that the number of erase loops has increased and meets a threshold) and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell (see para. 37 and 51, where if the threshold number of erase loops is met, the block may be converted from MLC type storage, which stores more bits per cell, to SLC type storage, which stores fewer bits per cell).
Lakshmi et al. and Yang et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Yang et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell., as taught by Yang al., in order to decrease wear and keep track of wear on memory (see Yang et al., para. 4-5, where keeping track of erase counts and comparing them to thresholds may lengthen the lifespan of a storage device).
As to claim 10, Lakshmi et al. and Yang et al. also disclose the method of claim 9, further comprising, during testing of the memory device, performing a data mis-compare check on the physical block after completing a successful erase verify operation on the physical block, separating the physical blocks on the memory device into categories based on the data mis-compare check, and storing a listing of the physical blocks with category markings in the non-volatile memory (see Lakshmi et al., para. 76-78, where during tests of the memory device, program and erase cycles are repeated to test for errors and memory elements or blocks are divided into categories based on the burn up test).
As to claim 11, Lakshmi et al. and Yang et al. also disclose the method of claim 10, further comprising placing physical blocks requiring more than one erase loop in a first category and physical blocks requiring one erase loop in a second category (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
As to claim 12, Lakshmi et al. and Yang et al. also disclose the method of claim 9, wherein forming comprises forming a first meta block to include physical blocks from the at least two dies with one erase cycle and forming a second meta block to include physical blocks from the at least two dies with two erase cycles (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
As to claim 15, Lakshmi et al. and Yang et al. also disclose the method of claim 9, wherein in dynamically recategorizing the physical block, the method comprises dynamically determining that the physical block should be placed in another category associated with a different number of erase loops when a parameter associated with a physical block increases, and increasing the weight assigned to the physical block (see Lakshmi et al., para. 104, where memory elements are tracked and the controller may modify block formations based on predicted block behavior and tracked parameters. In this case, an erase threshold would be different values for the PEC. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks, and therefore blocks would be recategorized into groups with different counts of erase loops depending on block parameter changes).
Referring to claim 17, Lakshmi et al. disclose as claimed, a method for forming a meta block in a storage device based on block erase loops, the storage device comprises a controller to execute the method comprising: during testing of a memory device, performing a data mis-compare check on a physical block after completing a successful erase verify operation on the physical block, separating physical blocks on the memory device into categories based on the data mis-compare check, and storing block data for the physical blocks with category markings in a non-volatile memory (see para. 76-78, where during tests of the memory device, program and erase cycles are repeated to test for errors and memory elements or blocks are divided into categories based on the burn up test); during use of the memory device, retrieving block data for physical blocks from the non-volatile memory (see fig. 2, showing both an on-die controller and a device controller. See para. 71-72, where blocks on separate dies may be grouped together to form a metablock); determining different categories of physical blocks on the memory device from the block data; identifying an erasure marking for a physical block from the block data; forming a meta block to include the physical blocks from the at least two dies, wherein the physical blocks in the meta block have a same erasure marking (see para. 72, where different blocks may be grouped together depending on their program and erase count, which would be different categories of physical blocks. The program and erase count, or PEC would be an erasure marking. Different blocks from different dies having the same PEC are grouped together into metablocks), and dynamically recategorizing and relinking the physical block to another meta block when a weight associated with the physical block exceeds an erase threshold (see para. 104, where memory elements are tracked and the controller may modify block formations based on predicted block behavior and tracked parameters. In this case, an erase threshold would be different values for the PEC).
Lakshmi et al. disclose the claimed invention except for where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell.
However, Yang et al. disclose where the erasure marking or erase threshold is erase loops or erase loop threshold (see para. 37, where erase loops are monitored and compared against an erase loop threshold); and wherein the controller confirms that the number of erase loops of the physical block has increased (see para. 37 and 51, where erase loops are monitored by the controller. See fig. 6a, 6b and 6c, showing an increase in erase loops with each erase operation), where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased (see para. 51, where the controller confirms that the number of erase loops has increased and meets a threshold) and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell (see para. 37 and 51, where if the threshold number of erase loops is met, the block may be converted from MLC type storage, which stores more bits per cell, to SLC type storage, which stores fewer bits per cell).
Lakshmi et al. and Yang et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Yang et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise where the erasure marking or erase threshold is erase loops or erase loop threshold; and wherein the controller confirms that the number of erase loops of the physical block has increased, where the physical blocks include a higher number of erase loops, and wherein the controller confirms that the erase loops of the physical block has increased and converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell and the controller moves the physical block between different pools based on the number of the erase loops of the physical block when the controller converts the physical block from the format storing more bits per cell to the format storing fewer bits per cell., as taught by Yang al., in order to decrease wear and keep track of wear on memory (see Yang et al., para. 4-5, where keeping track of erase counts and comparing them to thresholds may lengthen the lifespan of a storage device).
As to claim 18, Lakshmi et al. and Yang et al. also disclose the method of claim 17, further comprising placing physical blocks requiring more than one erase loop in a first category and physical blocks requiring one erase loop in a second category (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
As to claim 19, Lakshmi et al. and Yang et al. also disclose the method of claim 17, wherein forming comprises forming a first meta block to include physical blocks from the at least two dies with one erase cycle and forming a second meta block to include physical blocks from the at least two dies with two erase cycles (see Lakshmi et al., para. 71-72, where blocks having a program erase count of 1 are placed in one category and blocks having a program erase count of 2 are placed in a different category. Yang et al., para. 37 and 51 teaches that erase loop count may be used to categorize blocks).
Claims 5-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmi et al. and Yang et al. and in view of Marr (U.S. Patent No. 9,450,876), herein referred to as Marr.
As to claim 5, Lakshmi et al. and Yang et al. disclose the claimed invention except for the storage device of claim 1, wherein when the controller determines that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the controller uses the meta block having physical blocks in a category associated with multiple erase loops.
However, Marr discloses wherein when the controller determines that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the controller uses the meta block having physical blocks in a category associated with multiple erase loops (see col. 27-35, where host workloads are used in determining which memory device to utilize by selecting based on wear level. See col. 5, lines 62-67 and col. 6, lines 1-12, where workload is predicted and then if the workload requires very few cycles (not peak), then the workload may be directed to a device with high levels of wear. Blocks associated with multiple erase loops require more wear on the memory. Also see col. 11, lines 22-45, where wear levels on each drive are monitored and characterized based on metrics such as program erase count. When applied to Lakshmi, this would allow using metablocks in different categories based on host workload). .
Lakshmi et al. and Marr are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Marr, abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise wherein when the controller determines that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the controller uses the meta block having physical blocks in a category associated with multiple erase loops, as taught by Marr, in order to optimize for both performance and wear depending on current workloads.
As to claim 6, Lakshmi et al. and Yang et al. disclose the claimed invention except for the storage device of claim 1, wherein the controller dynamically chooses the meta block for host data, wherein in choosing the meta block, the controller determines a historical host data rate to select the meta block based on associated erase loops.
However, Marr discloses wherein the controller dynamically chooses the meta block for host data, wherein in choosing the meta block, the controller determines a historical host data rate to select the meta block based on associated erase loops. (see col. 27-35, where host workloads are used in determining which memory device to utilize by selecting based on wear level. See col. 5, lines 62-67 and col. 6, lines 1-12, where workload is predicted and then if the workload requires very few cycles (not peak), then the workload may be directed to a device with high levels of wear. Blocks associated with multiple erase loops require more wear on the memory. Also see col. 11, lines 22-45, where wear levels on each drive are monitored and characterized based on metrics such as program erase count. When applied to Lakshmi, this would allow using metablocks in different categories based on host workload). .
Lakshmi et al. and Marr are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Marr, abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise wherein the controller dynamically chooses the meta block for host data, wherein in choosing the meta block, the controller determines a historical host data rate to select the meta block based on associated erase loops., as taught by Marr, in order to optimize for both performance and wear depending on current workloads.
As to claim 13, Lakshmi et al. and Yang et al. disclose the claimed invention except for the method of claim 9, further comprising determining that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the method further comprising using the meta block having physical blocks in a category associated with multiple erase loops.
However, Marr discloses determining that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the method further comprising using the meta block having physical blocks in a category associated with multiple erase loops (see col. 27-35, where host workloads are used in determining which memory device to utilize by selecting based on wear level. See col. 5, lines 62-67 and col. 6, lines 1-12, where workload is predicted and then if the workload requires very few cycles (not peak), then the workload may be directed to a device with high levels of wear. Blocks associated with multiple erase loops require more wear on the memory. Also see col. 11, lines 22-45, where wear levels on each drive are monitored and characterized based on metrics such as program erase count. When applied to Lakshmi, this would allow using metablocks in different categories based on host workload). .
Lakshmi et al. and Marr are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Marr, abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise determining that a host workload is not at its peak and that using physical blocks requiring multiple erase loops do not cause a bottleneck for a given host workload, the method further comprising using the meta block having physical blocks in a category associated with multiple erase loops, as taught by Marr, in order to optimize for both performance and wear depending on current workloads.
As to claim 14, Lakshmi et al. and Yang et al. disclose the claimed invention except for the method of claim 9, further comprising dynamically choosing the meta block for host data, wherein in choosing the meta block, the method comprises determining a historical host data rate to select the meta block based on associated erase loops.
However, Marr discloses dynamically choosing the meta block for host data, wherein in choosing the meta block, the method comprises determining a historical host data rate to select the meta block based on associated erase loops (see col. 27-35, where host workloads are used in determining which memory device to utilize by selecting based on wear level. See col. 5, lines 62-67 and col. 6, lines 1-12, where workload is predicted and then if the workload requires very few cycles (not peak), then the workload may be directed to a device with high levels of wear. Blocks associated with multiple erase loops require more wear on the memory. Also see col. 11, lines 22-45, where wear levels on each drive are monitored and characterized based on metrics such as program erase count. When applied to Lakshmi, this would allow using metablocks in different categories based on host workload). .
Lakshmi et al. and Marr are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Marr, abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise dynamically choosing the meta block for host data, wherein in choosing the meta block, the method comprises determining a historical host data rate to select the meta block based on associated erase loops, as taught by Marr, in order to optimize for both performance and wear depending on current workloads.
Claims 8, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lakshmi et al. and Yang et al. and in view of Goss et al. (U.S. Patent Application Publication No. 2011/0302477), herein referred to as Goss et al.
As to claim 8, Lakshmi et al. and Yang et al. disclose the claimed invention except for the storage device of claim 1, wherein when the weight associated with the physical block exceeds the erase loop threshold, the controller converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell.
However, Goss et al. discloses wherein when the weight associated with the physical block exceeds the erase loop threshold, the controller converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell (see para. 64-66, where cells may be converted from MLC to SLC on demand depending on wear level. See para. 48, where a count of erase cycles may be used to determine wear level. A higher erase count would be associated with a high wear level).
Lakshmi et al. and Goss et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Goss et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise wherein when the weight associated with the physical block exceeds the erase loop threshold, the controller converts the physical block from a format storing more bits per cell to a format storing fewer bits per cell, as taught by Goss et al., in order to harden data to prevent data loss (see Goss et al., para. 2, regarding hardening data in order to prevent data loss and be more likely to recover information).
As to claim 16, Lakshmi et al. and Yang et al. disclose the claimed invention except for the method of claim 9, wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell.
However, Goss et al. discloses wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell (see para. 64-66, where cells may be converted from MLC to SLC on demand depending on wear level. See para. 48, where a count of erase cycles may be used to determine wear level. A higher erase count would be associated with a high wear level).
Lakshmi et al. and Goss et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Goss et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell, as taught by Goss et al., in order to harden data to prevent data loss (see Goss et al., para. 2, regarding hardening data in order to prevent data loss and be more likely to recover information).
As to claim 20, Lakshmi et al. and Yang et al. disclose the claimed invention except for the method of claim 17, wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell.
However, Goss et al. discloses wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell (see para. 64-66, where cells may be converted from MLC to SLC on demand depending on wear level. See para. 48, where a count of erase cycles may be used to determine wear level. A higher erase count would be associated with a high wear level).
Lakshmi et al. and Goss et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Lakshmi et al., abstract and Goss et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lakshmi et al. to comprise wherein when the weight associated with the physical block exceeds the erase loop threshold, the method comprises converting the physical block from a format storing more bits per cell to a format storing fewer bits per cell, as taught by Goss et al., in order to harden data to prevent data loss (see Goss et al., para. 2, regarding hardening data in order to prevent data loss and be more likely to recover information).
Response to Arguments
Applicant’s arguments, filed 2/19/26, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yang et al.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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