DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claim 19 be found allowable, claim 20 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Block et al., hereinafter Block, US Publication No. 2021/0159313.
Regarding Claim 1, Block teaches a computer-implemented method (Block paragraph [0003], wherein standard cell design methodologies with automatic placement and routing inherently utilize computers) for designing an integrated circuit, the method comprising:
placing a predefined cell within a twin-well CMOS silicon-on-insulator integrated circuit design (Block paragraphs [0023]-[0025], [0031] and [0036], wherein standard cells are placed in a CMOS design utilizing FDSOI, which include flipped and non-flipped well regions, i.e. twin-well), wherein the predefined cell comprises:
a logic region comprising one or more transistors of a first type, the first type being either conventional-well CMOS transistors or flipped-well CMOS transistors (Block Fig. 1 and Fig. 5 and paragraphs [0025] and [0035]-[0036], see non-flipped well region 154 having conventional CMOS transistors);
an inner set of boundary cells that are arranged along one or more edges of the logic region (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the non-flipped well region 154, e.g. 122, 124); and
an outer set of boundary cells that are arranged along one or more edges of the predefined cell and that are configured for placement adjacent transistors of a second type (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the flipped well region 156, e.g. 122, 126), the second type being either flipped-well CMOS transistors or conventional-well CMOS transistors and the second type being different from the first type (Block paragraph [0038], wherein the flipped well region 156 comprises flipped well CMOS transistors).
Regarding Claim 2, Block further teaches wherein the one or more transistors in the logic region are conventional-well CMOS transistors, and wherein the outer set of boundary cells are configured for placement adjacent flipped-well CMOS transistors (Block paragraphs [0035]-[0038], wherein the non-flipped well region contains conventional well CMOS transistors and the flipped well region contains flipped well CMOS transistors) .
Regarding Claim 3, Block further teaches wherein the boundary cells of the inner set form a continuous border around a perimeter of the logic region (Block Fig. 1 and Fig. 5 and paragraph [0025], wherein non-flipped well cells 102 are surrounded by flipped well cells 104, with the interposing region 152 between the non-flipped and flipped well regions indicating that there is a continuous border with the transistor cells closest to the border of the non-flipped well region).
Regarding Claim 4, Block further teaches wherein the boundary cells of the outer set form a continuous border around a perimeter of the predefined cell (Block Fig. 1 and Fig. 5 and paragraph [0025], wherein non-flipped well cells 102 are surrounded by flipped well cells 104, with the interposing region 152 between the non-flipped and flipped well regions indicating that there is a continuous border with the transistor cells closest to the border next to the flipped well region).
Regarding Claim 5, Block further teaches wherein each boundary cell of the outer set is separated from the logic region by at least one respective boundary cell of the inner set (Block Fig. 5, wherein the cells of the outer set, i.e. 122 and 126 are separated from the non-flipped well region by cells of the inner set, i.e. 122 and 124).
Regarding Claim 6, Block further teaches wherein the predefined cell comprises a spacing region arranged between the inner set of boundary cells and the outer set of boundary cells (Block Fig. 6 and paragraphs [0039]-[0040], wherein there is a doped barrier region 170 that provides a spacing between the inner and outer set of boundary cells).
Regarding Claim 7, Block further teaches wherein the spacing region is a single continuous region that fully encloses the logic region and the inner set of boundary cells (Block Fig. 1 and Fig. 6, wherein the presence of the interposing region between the non-flipped well and flipped well regions results in a full enclosed non-flipped well region comprising a continuous doped barrier region).
Regarding Claim 8, Block further teaches wherein at least one of the one or more transistors in the logic region abuts a boundary cell of the inner set (Block Fig. 5, wherein at least one of the transistors of the non-flipped well region, e.g. 160 or 162, abuts the one or more transistors of the inner set).
Regarding Claim 9, Block further teaches retrieving the predefined cell from a cell library database (Block paragraph [0023], wherein the cells are from a library).
Regarding Claim 10, Block further teaches comprising placing a plurality of instances of the predefined cell within the twin-well CMOS silicon-on-insulator integrated circuit design (Block Fig. 5, wherein there are a plurality of instances of the non-flipped well transistors and interposing region transistors).
Regarding Claim 11, Block further teaches generating a placed-gates netlist for the twin-well CMOS silicon-on-insulator integrated circuit design (Block paragraphs [0003] and [0020], wherein placement and routing generates a layout and corresponding placed netlist).
Regarding Claim 12, Block further teaches placing the predefined cell within a region that is designated for transistors of the second type (Block Fig. 5, wherein the instances of the non-flipped well cells in conjunction with the instances of the cells in the interposing region are placed within areas having the flipped well cell structures).
Regarding Claim 13, Block further teaches comprising placing the predefined cell as an independent power domain that is different from a power domain within which the predefined cell is placed (Block paragraphs [0034] and [0043], wherein there are various separate power rails placed within the design corresponding to separate power domains).
Regarding Claim 14, Block further teaches wherein the logic region contains only a single row of one or more transistors (Block Fig. 5 and paragraph [0037], wherein the non-flipped well region comprises a row of transistors).
Regarding Claim 15, Block further teaches wherein the logic region contains only transistors of the first type (Block paragraph [0036], wherein the non-flipped well region only contains non-flipped well transistors).
Regarding Claim 16, Block further wherein the one or more transistors are arranged to perform a Boolean logic function or to provide a flip-flop, latch or buffer (Block paragraph [0023], wherein the transistors form logic functions or storage functions).
Regarding Claim 17, Block further teaches a non-transitory computer-readable medium storing computer software (Block paragraph [0003], wherein standard cell design methodologies with automatic placement and routing inherently utilize computers having memory containing instructions) for designing an integrated circuit comprising instructions that, when executed by a processor, cause the processor to perform the method of claim 1.
Regarding Claim 18, Block further teaches a computer system comprising a processor and a memory and configured to perform the method of claim 1 (Block paragraph [0003], wherein standard cell design methodologies with automatic placement and routing inherently utilize computers having processors and memory containing instructions).
Regarding Claim 19, Block teaches a non-transitory computer-readable medium storing data (Block paragraph [0003], wherein standard cell design methodologies with automatic placement and routing inherently utilize computers having memory containing instructions) that represents a predefined cell for a twin-well CMOS silicon-on-insulator integrated circuit design (Block paragraphs [0023]-[0025], [0031] and [0036], wherein standard cells are placed in a CMOS design utilizing FDSOI, which include flipped and non-flipped well regions, i.e. twin-well), wherein the predefined cell comprises:
a logic region comprising one or more transistors of a first type, the first type being either conventional-well CMOS transistors or flipped-well CMOS transistors (Block Fig. 1 and Fig. 5 and paragraphs [0025] and [0035]-[0036], see non-flipped well region 154 having conventional CMOS transistors);
an inner set of boundary cells that are arranged along one or more edges of the logic region (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the non-flipped well region 154, e.g. 122, 124); and
an outer set of boundary cells that are arranged along one or more edges of the predefined cell and that are configured for placement adjacent transistors of a second type (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the flipped well region 156, e.g. 122, 126), the second type being either flipped-well CMOS transistors or conventional-well CMOS transistors and the second type being different from the first type (Block paragraph [0038], wherein the flipped well region 156 comprises flipped well CMOS transistors).
Regarding Claim 20, Block teaches a non-transitory computer-readable medium storing data (Block paragraph [0003], wherein standard cell design methodologies with automatic placement and routing inherently utilize computers having memory containing instructions) that represents a twin-well CMOS silicon-on-insulator integrated circuit design comprising a predefined cell (Block paragraphs [0023]-[0025], [0031] and [0036], wherein standard cells are placed in a CMOS design utilizing FDSOI, which include flipped and non-flipped well regions, i.e. twin-well), wherein the predefined cell comprises:
a logic region comprising one or more transistors of a first type, the first type being either conventional-well CMOS transistors or flipped-well CMOS transistors (Block Fig. 1 and Fig. 5 and paragraphs [0025] and [0035]-[0036], see non-flipped well region 154 having conventional CMOS transistors);
an inner set of boundary cells that are arranged along one or more edges of the logic region (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the non-flipped well region 154, e.g. 122, 124); and
an outer set of boundary cells that are arranged along one or more edges of the predefined cell and that are configured for placement adjacent transistors of a second type (Block Fig. 1 and Fig. 5 and paragraphs [0035]-[0036], wherein a group of transistor cells 120 are placed in a region 152 between the non-flipped well region 154 and the flipped well region 156, with a set of transistor cells along the edge of the flipped well region 156, e.g. 122, 126), the second type being either flipped-well CMOS transistors or conventional-well CMOS transistors and the second type being different from the first type (Block paragraph [0038], wherein the flipped well region 156 comprises flipped well CMOS transistors).
Examiner notes that regarding Claims 19 and 20, the claims are directed towards nonfunctional descriptive material, as the computer-readable medium in each of the claims merely serves as a support for information or data, with no functional relationship existing. As such, the limitations are owed no patentable weight and have been examined as such.
Conclusion
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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