DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8-9, 12-13, and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication Number 2008/0158283 to Penning (“Penning”), knowledge commonly known in the art as evidenced by US Patent Application Publication Number 2014/0215228 to Choon et al. (“Choon”) and admitted by Applicant to be prior art, and US Patent Application Publication Number 2019/0327099 to Vanich et al. (“Vanich”).
In reference to Claim 1, Penning discloses a system for providing power over Ethernet (PoE) (See Paragraphs 8 and 33), comprising: a network interface device (See Figure 1 Number 105 and Paragraph 31) including: a first power jack (See Figure 3 Number 115 and Paragraphs 34 and 38) configured to establish a first power connection with a power adapter (See Figure 3 Number 390 and Paragraphs 38 and 49); a first data port (See Figure 3 Number 320) and configured to establish a first communication link between the network interface device and a first external device (See Figure 1 Number 110), wherein the first communication link enables an exchange of data and sourcing of power with the first external device (See Paragraphs 30, 47, and 49); a second data port (See Figure 3 Number 315) configured to establish a second communication link between the network interface device and a second external device (See Figure 1 Number 125-1), wherein the second communication link enables an exchange of data with the second external device (See Paragraphs 30 and 47-48); and a first switching circuit communicatively coupled to the first data port and the second external device (See Figure 3 Number 380), wherein the first switching circuit includes a first switch and is configured to control sourcing of power by opening or closing the first switch based on a source of the power (See Figure 3 Number 380 and Paragraph 51), wherein the first switch is closed responsive to power received at the first data port (See Paragraph 56), and wherein the first switch is opened responsive to power received at the first power jack, wherein opening the first switch responsive to power received at the first power jack inhibits the power being received at the first power jack from flowing to a powered device (PD) chipset of the network device (See Figure 3 Number 360 and Paragraphs 52 and 56 [PoE controller 360 is an integrated circuit chip that provides power signatures and other power allocation communication to an upstream PoE PSE, and is thus a PD chipset in accordance with the broadest reasonable interpretation of the term; switching circuit 380 inhibits power received at the first power jack 115 from reaching PD chipset 360 in the event of a reverse bias diode breakdown of diodes 385]). Penning further discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31), but does not explicitly disclose that the network interface device is a network interface card (NIC). Official Notice is taken the implementing a network switch as a network interface card is well known in the art, as evidenced by Choon (See Figure 3b and Paragraph 39). This has been admitted by Applicant to be prior art. Penning further discloses the use of a combined PoE data and power connection for providing power and data to the second external device (See Paragraphs 47 and 53), but does not explicitly disclose a second power jack configured to establish a second power connection between the network interface device and the second external device, wherein the second power jack is configured to provide power to the second external device. Vanich discloses a PoE network interface device (See Figure 1 Number 120) for receiving a combined PoE data and power connection (See Figure 1 Number 121 and Paragraphs 17 and 19) and providing a second data port (See Figure 1 Number 122) configured to establish a second communication link between the network interface device and a second external device (See Figure 1 Number 125-1), wherein the second communication link enables an exchange of data with the second external device (See Paragraphs 19 and 22); and a second power jack (See Figure 1 Number 123) configured to establish a second power connection between the network interface device and the second external device, wherein the second power jack is configured to provide power to the second external device (See Paragraphs 19 and 21).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning using a well-known network interface card to implement the network switch interface device, and using the separate data interface and power jack of Vanich to connect to the second external device, resulting in the invention of Claim 1, because Penning discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31 of Penning), and the simple substitution of the well-known network switch interface card to implement the network switch interface device of Penning would have yielded the predictable result of allowing the network switch interface device to be easily removable (See Paragraph 39 of Choon), thus allowing for easier modifications and repairs; and in order to yield the predictable result of enabling the second external device to benefit from a PoE supply of data and power even if it is not PoE enabled (See Paragraph 19 of Vanich).
In reference to Claim 3, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the NIC is coupled directly to the first external device and the second external device (See Figure 1), wherein the NIC facilitates the exchange of data and the sourcing of power between the first external device and the second external device (See Paragraphs 30, 47, and 49).
In reference to Claim 4, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the first switch is a ground switch or a power switch (See Figure 3 [a switch is coupled along a power line of PoE supply and a switch is coupled along the ground line of a PoE supply; “ground switch” and “power switch have been interpreted in accordance with Applicant’s disclosure in Figure 5 and Paragraph 43]).
In reference to Claim 5, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the first switching circuit includes a second switch, wherein the first switch is a ground switch and the second switch is a power switch (See Figure 3 [a switch is coupled along a power line of PoE supply and a switch is coupled along the ground line of a PoE supply; “ground switch” and “power switch have been interpreted in accordance with Applicant’s disclosure in Figure 5 and Paragraph 43]).
In reference to Claim 6, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the first external device operates as power sourcing equipment (PSE) (See Paragraphs 30-31 and 33-34) and the second external device operates as a PD, wherein the NIC is configured to receive power from the first external device and source the power to the second external device (See Paragraphs 30, 47, and 49).
In reference to Claim 8, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the first external device operates as PSE and the NIC operates as a PD (See Paragraphs 30-31 and 33-34), wherein the NIC is configured to receive power from the first external device and source the power to the second external device (See Paragraphs 30, 47, and 49).
In reference to Claim 9, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the NIC further includes: a PSE chipset configured to merge a first DC power signal and a data signal (See Figure 3 Numbers 305, 330, and 370 and Paragraphs 30, 47-48, and 53); and the PD chipset including a DC-to-DC converter configured to convert the voltage from a second DC power signal to a third DC power signal, wherein the second DC power signal voltage is greater than the third DC power signal voltage (See Paragraphs 33 [in order to comply with the PoE standards, a device providing voltage over a PoE interface must initially provide a voltage between 2.7 and 10.1 volts so as to prevent damage to non PoE devices; as a PoE input during normal operation is 44-57 volts and a PoE output during normal operation is 37-57 volts, there must necessarily be a DC-DC converter to convert the voltage of the received PoE power to the lower initially required voltage]).
In reference to Claim 12, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the first data port is associated with a first Ethernet transformer, wherein the first Ethernet transformer is configured to separate data signals and power signals received at the first data port (See Figure 3 Number 335 and Paragraph 47).
In reference to Claim 13, Penning discloses a network interface device (See Figure 1 Number 105 and Paragraph 31) for providing power over Ethernet (PoE) (See Paragraphs 8 and 33), the network interface device comprising: a first power jack (See Figure 3 Number 115 and Paragraphs 34 and 38) configured to establish a first power connection with a power adapter (See Figure 3 Number 390 and Paragraphs 38 and 49); a first data port (See Figure 3 Number 320) and configured to establish a first communication link between the network interface device and a first external device (See Figure 1 Number 110), wherein the first communication link enables an exchange of data and sourcing of power (See Paragraphs 30, 47, and 49); a second data port a second data port (See Figure 3 Number 315) configured to establish a second communication link between the network interface device and a second external device (See Figure 1 Number 125-1), wherein the second communication link enables an exchange of data with the second external device (See Paragraphs 30 and 47-48); a power sourcing equipment (PSE) chipset configured to merge data and power signals (See Paragraphs 30 and 47-48); a powered device (PD) chipset configured to convert the voltage of power received at the first power jack from a first DC power signal voltage to a second DC power signal voltage, wherein the first DC power signal voltage is greater than the second DC power signal voltage (See Paragraph 33 [in order to comply with the PoE standards, a device providing voltage over a PoE interface must initially provide a voltage between 2.7 and 10.1 volts so as to prevent damage to non PoE devices; as a PoE input during normal operation is 44-57 volts and a PoE output during normal operation is 37-57 volts, there must necessarily be a DC-DC converter to convert the voltage of the received PoE power to the lower initially required voltage]); and a first switching circuit configured to control sourcing of power (See Figure 3 Number 380 and Paragraph 51), and wherein, when the first power jack receives power, a first switch of the first switching circuit is opened to inhibit the power being received at the first power jack from flowing to a powered device (PD) chipset of the network device (See Figure 3 Number 360 and Paragraphs 52 and 56 [PoE controller 360 is an integrated circuit chip that provides power signatures and other power allocation communication to an upstream PoE PSE, and is thus a PD chipset in accordance with the broadest reasonable interpretation of the term; switching circuit 380 inhibits power received at the first power jack 115 from reaching PD chipset 360 in the event of a reverse bias diode breakdown of diodes 385]), and wherein, when the first data port receives power, the first switch of the first switching circuit is closed to source the power received at the first data port to the second external device (See Paragraph 56). Penning further discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31), but does not explicitly disclose that the network interface device is a network interface card (NIC). Official Notice is taken the implementing a network switch as a network interface card is well known in the art, as evidenced by Choon (See Figure 3b and Paragraph 39). This has been admitted by Applicant to be prior art. Penning further discloses the use of a combined PoE data and power connection for providing power and data to the second external device (See Paragraphs 47 and 53), but does not explicitly disclose a second power jack configured to establish a second power connection between the NIC and the second external device, wherein the second power jack is configured to provide power to the second external device. Vanich discloses a PoE network interface device (See Figure 1 Number 120) for receiving a combined PoE data and power connection (See Figure 1 Number 121 and Paragraphs 17 and 19) and providing a second data port (See Figure 1 Number 122) configured to establish a second communication link between the network interface device and a second external device (See Figure 1 Number 125-1), wherein the second communication link enables an exchange of data with the second external device (See Paragraphs 19 and 22); and a second power jack (See Figure 1 Number 123) configured to establish a second power connection between the network interface device and the second external device, wherein the second power jack is configured to provide power to the second external device (See Paragraphs 19 and 21).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning using a well-known network interface card to implement the network switch interface device, and using the separate data interface and power jack of Vanich to connect to the second external device, resulting in the invention of Claim 13, because Penning discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31 of Penning), and the simple substitution of the well-known network switch interface card to implement the network switch interface device of Penning would have yielded the predictable result of allowing the network switch interface device to be easily removable (See Paragraph 39 of Choon), thus allowing for easier modifications and repairs; and in order to yield the predictable result of enabling the second external device to benefit from a PoE supply of data and power even if it is not PoE enabled (See Paragraph 19 of Vanich).
In reference to Claim 15, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 13 above. Penning further discloses that the NIC is configured to operate in a PSE mode or a PD mode (See Paragraphs 30, 47, and 49).
In reference to Claim 16, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 15 above. Penning further discloses that when the NIC operates in a PSE mode, power and data signals are merged via the PSE chipset (See Paragraphs 30 and 47-48) and when the NIC operates in the PD mode, the voltage of power is converted via the PD chipset (See Paragraph 33 [in order to comply with the PoE standards, a device providing voltage over a PoE interface must initially provide a voltage between 2.7 and 10.1 volts so as to prevent damage to non PoE devices; as a PoE input during normal operation is 44-57 volts and a PoE output during normal operation is 37-57 volts, there must necessarily be a DC-DC converter to convert the voltage of the received PoE power to the lower initially required voltage]).
Claim(s) 2, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Penning, knowledge commonly known in the art, and Vanich as applied to Claims 1 and 8 above, and further in view of US Patent Application Publication Number 2019/0253268 to Fu et al. (“Fu”).
In reference to Claim 2, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that when the first switch included in the first switching circuit is closed, power is sourced to the second external device via the second power jack (See Paragraph 56); and wherein, when the first switch included in the first switching circuit is open, power is not received from the first external device via the first data port (See Paragraph 56). However, Penning does not explicitly disclose that when the first switch included in the first switching circuit is open, power is sourced to the first external device via the first data port. Fu discloses a bidirectional PoE network interface device, wherein when power is not available from a first power jack, power is sourced via a first data port from a first network device to a second external device (See Paragraphs 74-77); and wherein, when power is available from the first power jack, power is sourced from the first power jack to the first external device via a first data port (See Paragraphs 71-73).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning, knowledge commonly known in the art, and Vanich using the bidirectional PoE capability to both supply and receive power from the first external device based on the availability of power at the first power jack, resulting in the invention of Claim 2, in order to yield the predictable result of providing redundancy in power supply, thus allowing devices to continue operating in the event of a power failure (See Paragraphs 5 and 13 of Fu).
In reference to Claim 7, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning does not explicitly disclose that the first external device operates as a PD and the NIC operates as PSE, wherein the NIC is configured to receive power from the power adapter and source the power to the first external device. Fu discloses a bidirectional PoE network interface device, wherein when power is available from a first power jack, the device operates as a PSE and a first network device operates as a PD, and power is sourced from the first power jack to the first external device via a first data port (See Paragraphs 71-73).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning, knowledge commonly known in the art, and Vanich using the bidirectional PoE capability to both supply and receive power from the first external device based on the availability of power at the first power jack, resulting in the invention of Claim 7, in order to yield the predictable result of providing redundancy in power supply, thus allowing devices to continue operating in the event of a power failure (See Paragraphs 5 and 13 of Fu).
In reference to Claim 10, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 9 above. Penning further discloses that the PD chipset is configured to receive the second DC power signal from the first data port and source the third DC power signal to the second external device via the second power jack (See Paragraphs 30 and 47-48). Penning does not explicitly disclose that the PSE chipset (See Figure 3 Number 303) is configured to receive the first DC power signal from the first power jack, merge the first DC power signal with the data signal as a combined power-data signal, and source the combined power-data signal to the first external device via the first data port. Fu discloses a bidirectional PoE network interface device, wherein a the PSE chipset is configured to receive a first DC power signal from a first power jack (See Paragraphs 38 and 49), merge the first DC power signal with the data signal as a combined power-data signal (See Paragraphs 71-72 [PoE necessarily merges a power signal and a data signal into a combined power-data signal]), and source the combined power-data signal to the first external device via the first data port (See Paragraphs 71).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning, knowledge commonly known in the art, and Vanich using the bidirectional PoE capability to both supply and receive power from the first external device based on the availability of power at the first power jack, resulting in the invention of Claim 10, in order to yield the predictable result of providing redundancy in power supply, thus allowing devices to continue operating in the event of a power failure (See Paragraphs 5 and 13 of Fu).
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Penning, knowledge commonly known in the art, and Vanich as applied to Claims 1 and 13 above, and further in view of knowledge commonly known in the art, as evidenced by CTC News Article “Reverse Current Protection” (“CTC”) and admitted by Applicant to be prior art..
In reference to Claim 11, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 1 above. Penning further discloses that the NIC further includes: a diode circuit including a diode switchable between an open state and a closed state based on whether power is present at the first power jack, wherein the first switching circuit and the diode circuit are configured to control sourcing of power based on the source of power (See Figure 3 Number 385 and Paragraph 51), and wherein, when power is present at the first power jack, the first switch is open and the diode is closed (See Paragraph 51); when power is absent at the first power jack and power is present at the first data port, the first switch is closed and the diode is open (See Paragraph 51). However, Penning does not explicitly disclose that the NIC further includes: a second switching circuit including a second switch switchable between an open state and a closed state based on whether power is present at the first power jack, wherein the first switching circuit and the second switching circuit are configured to control sourcing of power based on the source of power, and wherein, when power is present at the first power jack, the first switch is open and the second switch is closed; when power is absent at the first power jack and power is present at the first data port, the first switch is closed and the second switch is open; and when power is absent at the first power jack and power is absent at the first data port, the first switch is open and the second switch is open. Official Notice is taken that using a switching circuit in place of a diode to prevent reverse flow of power is well known in the art, as evidenced by CTC (See Pages 2-3 Section 2). This has been admitted by Applicant to be prior art. Furthermore, there are a finite number of states that the first and second switches can be in – both open, both closed, or one open and one closed. One of ordinary skill in the art would recognize that the particular state of the switch is irrelevant when there is no power supplied from either the first power jack or the first data port, as there is no power available to source or block.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning, knowledge commonly known in the art, and Vanich using a well-known switching circuit in place of the diode circuit, and placing both switches in an open state when power is absent from both the first power jack and the first data port, resulting in the invention of Claim 11, because the simple substitution of a switching circuit in place of a diode to prevent reverse power flow would have yielded the predictable result of providing lower positive conduction voltage and higher allowed current with lower power loss than diodes (See Page 3 Section ‘Back-to-Back MOSFETs’ of CTC); and because one of ordinary skill in the art has good reason to pursue known options from a finite number of options within their technical grasp in an attempt to provide an improved construction of the device of Penning.
In reference to Claim 14, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 13 above. Penning further discloses that the NIC further includes: a diode circuit including a diode switchable between an open state and a closed state based on whether power is present at the first power jack, wherein the first switching circuit and the diode circuit are configured to control sourcing of power based on the source of power (See Figure 3 Number 385 and Paragraph 51), and wherein, when power is present at the first power jack, the first switch is open and the diode is closed (See Paragraph 51); when power is absent at the first power jack and power is present at the first data port, the first switch is closed and the diode is open (See Paragraph 51). However, Penning does not explicitly disclose that the NIC further includes: a second switching circuit including a second switch switchable between an open state and a closed state based on whether power is present at the first power jack, wherein the first switching circuit and the second switching circuit are configured to control sourcing of power based on the source of power, and wherein, when power is present at the first power jack, the first switch is open and the second switch is closed; when power is absent at the first power jack and power is present at the first data port, the first switch is closed and the second switch is open; and when power is absent at the first power jack and power is absent at the first data port, the first switch is open and the second switch is open. Official Notice is taken that using a switching circuit in place of a diode to prevent reverse flow of power is well known in the art, as evidenced by CTC (See Pages 2-3 Section 2). This has been admitted by Applicant to be prior art. Furthermore, there are a finite number of states that the first and second switches can be in – both open, both closed, or one open and one closed. One of ordinary skill in the art would recognize that the particular state of the switch is irrelevant when there is no power supplied from either the first power jack or the first data port, as there is no power available to source or block.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning, knowledge commonly known in the art, and Vanich using a well-known switching circuit in place of the diode circuit, and placing both switches in an open state when power is absent from both the first power jack and the first data port, resulting in the invention of Claim 14, because the simple substitution of a switching circuit in place of a diode to prevent reverse power flow would have yielded the predictable result of providing lower positive conduction voltage and higher allowed current with lower power loss than diodes (See Page 3 Section ‘Back-to-Back MOSFETs’ of CTC); and because one of ordinary skill in the art has good reason to pursue known options from a finite number of options within their technical grasp in an attempt to provide an improved construction of the device of Penning.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Penning and knowledge commonly known in the art as evidenced by Choon and admitted by Applicant to be prior art..
In reference to Claim 17, Penning discloses a method for providing power over Ethernet (PoE) (See Paragraphs 8 and 33), comprising: establishing, via a first power jack (See Figure 3 Number 115 and Paragraphs 34 and 38) of a network interface device (See Figure 1 Number 105 and Paragraph 31), a first power connection with a power adapter (See Figure 3 Number 390 and Paragraphs 38 and 49); establishing, via a first data port (See Figure 3 Number 320) of the network interface device, a first communication link between the network interface device and a first external device (See Figure 1 Number 110), wherein the first communication link enables an exchange of data and sourcing of power (See Paragraphs 30, 47, and 49); and controlling, via a first switching circuit (See Figure 3 Number 380) of the network interface device, sourcing of power based on a source of power (See Paragraph 51) by: opening a first switch included in the first switching circuit responsive to power being received at the first power jack to inhibit the power being received at the first power jack from flowing to a powered device (PD) chipset of the network device (See Figure 3 Number 360 and Paragraphs 52 and 56 [PoE controller 360 is an integrated circuit chip that provides power signatures and other power allocation communication to an upstream PoE PSE, and is thus a PD chipset in accordance with the broadest reasonable interpretation of the term; switching circuit 380 inhibits power received at the first power jack 115 from reaching PD chipset 360 in the event of a reverse bias diode breakdown of diodes 385]); and closing the first switch included in the first switching circuit responsive to power being received at the first data port to enable the power being received at the first data port to flow to the PD chipset of the network interface device (See Paragraph 56). Penning further discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31), but does not explicitly disclose that the network interface device is a network interface card (NIC). Official Notice is taken the implementing a network switch as a network interface card is well known in the art, as evidenced by Choon (See Figure 3b and Paragraph 39). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning using a well-known network interface card to implement the network switch interface device, resulting in the invention of Claim 17, because Penning discloses that the network interface device can be any type of network device, including a network switch (See Paragraph 31 of Penning), and the simple substitution of the well-known network switch interface card to implement the network switch interface device of Penning would have yielded the predictable result of allowing the network switch interface device to be easily removable (See Paragraph 39 of Choon), thus allowing for easier modifications and repairs.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Penning and knowledge commonly known in the art as applied to Claim 17 above, and further in view of Vanich.
In reference to Claim 18, Penning and knowledge commonly known in the art disclose the limitations as applied to Claim 17 above. Penning further discloses establishing, via a combined PoE data and power connection for providing power and data to the second external device, a second power connection between the NIC and a second external device (See Paragraphs 47 and 53); and establishing, via a second data port of the NIC, a second communication link between the NIC and the second external device (See Paragraphs 47 and 53). However, Penning does not explicitly disclose establishing, via a second power jack of the NIC, a second power connection between the NIC and a second external device. Vanich discloses the a PoE network interface device (See Figure 1 Number 120) for receiving a combined PoE data and power connection (See Figure 1 Number 121 and Paragraphs 17 and 19) and establishing, via a second power jack (See Figure 1 Number 123), a second power connection between the network interface device and a second external device (See Paragraphs 19 and 21); and establishing, via a second data port of the network interface device (See Figure 1 Number 122), a second communication link between the network interface device and the second external device (See Paragraphs 19 and 22).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning and knowledge commonly known in the art using the separate data interface and power jack of Vanich to connect to the second external device, resulting in the invention of Claim 18, in order to yield the predictable result of enabling the second external device to benefit from a PoE supply of data and power even if it is not PoE enabled (See Paragraph 19 of Vanich).
In reference to Claim 19, Penning, knowledge commonly known in the art, and Vanich disclose the limitations as applied to Claim 18 above. Penning further discloses receiving, at the first data port of the NIC, a set of signals from the first external device, the set of signals including a power signal and a data signal (See Paragraphs 30, 47, and 49); splitting, via a transformer associated with the first data port, the set of signals into the power signal and the data signal (See Figure 3 Number 335 and Paragraph 47). Vanich further discloses transmitting, via the second power jack of the NIC, the power signal to the second external device (See Paragraphs 19 and 21); and transmitting, via the second data port of the NIC, the data signal to the second external device (See Paragraphs 19 and 22).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Penning and knowledge commonly known in the art as applied to Claim 17 above, and further in view of Fu.
In reference to Claim 20, Penning and knowledge commonly known in the art disclose the limitations as applied to Claim 17 above. Penning further discloses receiving, at the first power jack of the NIC, a first power signal from a power adapter (See Figure 3 Number 390 and Paragraphs 38 and 49). However, Penning does not explicitly disclose merging, with a power sourcing equipment (PSE) chipset included in the NIC, the first power signal with a data signal as a combined power-data signal; and transmitting, via the first data port of the NIC, the combined power-data signal to the first external device. Fu discloses a bidirectional PoE network interface device; receiving, at a first power jack of a network interface device, a first power signal from a power adapter (See Paragraph 71); merging, with a power sourcing equipment (PSE) chipset included in the network interface device (See Figure 3 Number 303), the first power signal with a data signal as a combined power-data signal (See Paragraphs 71-72 [PoE necessarily merges a power signal and a data signal into a combined power-data signal]); and transmitting, via a first data port of the network interface device (See Figure 3 Number 311), the combined power-data signal to the first external device (See Paragraphs 71).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Penning and knowledge commonly known in the art, using the bidirectional PoE capability to both supply and receive power from the first external device based on the availability of power at the first power jack, resulting in the invention of Claim 20, in order to yield the predictable result of providing redundancy in power supply, thus allowing devices to continue operating in the event of a power failure (See Paragraphs 5 and 13 of Fu).
Response to Arguments
Applicant’s arguments, see Pages 9-11, filed 28 April 2026, with respect to the objections to the drawings have been fully considered and are persuasive in light of Applicant’s amendments. The objections to the drawings have been withdrawn.
Applicant's arguments filed 28 April 2026 with respect to the prior art rejections have been fully considered but they are not persuasive.
Applicant has argued that Penning does not disclose that the opening the first switch responsive to power received at the first power jack inhibits the power being received at the first power jack from flowing to a PD chipset of the NIC (See Pages 12-15). In response, the Examiner notes that Penning discloses that the first switch 380 is opened responsive to power received at the first power jack (See Paragraph 56), wherein opening the first switch responsive to power received at the first power jack inhibits the power being received at the first power jack from flowing to a powered device (PD) chipset 360 of the network device (See Figure 3 Number 360 and Paragraphs 52 and 56), as the first switch 380 inhibits power received at the first power jack 115 from reaching the PD chipset 360 in the event of a reverse bias diode breakdown of diodes 385. As Applicant has admitted, “Penning expressly describes that switching circuit 380…is opened to: source power from the independent power supply 115…and prevent current from flowing from uplink port 320” (See Page 14 Lines 1-3). As one of ordinary skill in the art would recognize, an electrical switch inhibits/prevents any flow of power through it, regardless of direction, and thus, if current is inhibited from flowing from the uplink port 320 and PD chipset 360, current is likewise inhibited from flowing to the uplink port 320 and PD chipset 360.
Applicant has argued that Penning does not disclose preventing current from flowing from the independent power supply 115 (See Page 14). In response, the Examiner notes that the claims require only that opening the first witch inhibits power being received at the first power jack from flowing to a PD chipset of the NIC, and does not require all current flow from the first power jack to be inhibited, nor does it preclude current flow from the first power jack from being provided to other elements. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
Prosecution Insights