DETAILED ACTION
Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
09/02/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 02/20/2026. Claims 1-
20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4,7-8,10-13 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 20200151106 A1) in view of Lu et al. (US 20230280929 A1) and further in view of SHIN et al. (US 20230289083 A1) hereinafter Ahn and Lu and SHIN.
Regarding claim 1, Ahn teaches An apparatus, comprising: a non volatile memory device comprising a first controller; and a second controller coupled with the non-volatile memory device, wherein the second controller is configured to cause the apparatus to: (“a processor of the storage device 100, including the memory controller 120 and/or the non-volatile memory 110, and/or the host 200 may include, but are not limited to, a central processing unit (CPU)”) (paragraph [0027], line 4-6) (i.e. Fig 1 illustrates storage device 100 having host 200 with CPU or first controller and memory controller 120 as second controller)
transfer, in response to issuing the command, a first portion of the data stored at a first plane of the set of planes to the second controller; and transfer, in response to issuing the command, a second portion of the data stored at a second plane of the set of planes to the second controller. (“The NVM 110 may transmit the plurality of portions of page data including the first page data to the memory controller 120 (S124). In this example, the first page data includes page data sensed from the first plane. Based on the data output command set, the NVM 110 may output the first page data of the first plane, and thereafter change the plane on which the page data is output to output page data of another plane. That is, the NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes”) (paragraph [0050], line 1-5) (i.e. Fig 2 step S124 illustrates NVM 110 110 may transmit or transfer the plurality of portions of page data including the first page data to the memory controller 120 and based on data output command set NVM 110 may output from first plane to another plane. In other words, NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes)
Ahn teaches memory device with multi plane data transfer. However, Ahn does not explicitly teach the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence,
automatically switch between the respective planes in accordance with the sequence
On the other hand, Lu which also relates to memory device with multi plane data transfer teaches
the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence (see Fig 10, paragraph [0108], illustrates address control circuit 1112 can control the row address decoder 1108 and column address decoder 1109 automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array)
automatically switch between the respective planes in accordance with the sequence (see Fig 13, paragraph [0115], illustrates automatic switching is done according to command sequence confirming address switching for multi plane)
Both Ahn and Lu relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and Lu, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn with Lu by incorporating memory device with multi plane data transfer in response to command from host, as taught by Lu, to enable automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array where switching is done according to command sequence confirming address switching for multi plane. The combined system of Ahn - Lu allows performing a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller as mentioned in paragraph [0005]. Therefore, the combination of Ahn - Lu improves performance of the flash memory device. See Lu, paragraph [0117].
Ahn in view of Lu and teaches memory device with multi plane data transfer. However, Ahn - Lu combination does not explicitly teach write, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes;
determine to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes;
issue, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written,
On the other hand, SHIN which also relates to memory device with multi plane data transfer teaches write, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes; (see Fig 1A and 2B, paragraph [0065], illustrates data is sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150)
determine to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes; (see Fig 2A and 2B, paragraph [0060], illustrates read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in any one of the memory devices 150 to 153)
issue, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written, the portions of the data stored at respective planes of the set of planes to the second controller; (see Fig 1A and 2B, paragraph [0065], illustrates read commands are sequentially generated or issued according to the order of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150 as they were written in sequence)
Both Ahn, Lu and SHIN relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and see Lu, abstract, and SHIN, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn - Lu combination with SHIN by incorporating memory device with multi plane data transfer in response to command from host, as taught by SHIN, to enable data to be sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device and read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 read commands are sequentially generated or issued according to the order of planes as they were written. The combined system of Ahn – Lu - SHIN allows a method which may include: performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, and storing the received data as mentioned in paragraph [0006]. Therefore, the combination of Ahn - Lu - SHIN improves operational reliability and communication performance. See SHIN, paragraph [0042].
Regarding claim 2, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 1. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 1, wherein the second controller is further configured to cause the apparatus to: issue, to the first controller based at least in part on the determination, a second command to sense the data
transfer, in response to the second command, the first portion of the data from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transfer, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The apparatus of claim 1, wherein the second controller is further configured to cause the apparatus to: issue, to the first controller based at least in part on the determination, a second command to sense the data; (“The NVM 110 ma, sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers (at least two page buffers) respectively connected to the plurality of planes (S122) based on the multi-plane read command set”) (paragraph [0046], line 2-4) (i.e. Fig 2 step S122 illustrates after the command is transmitted in step S121, NVM 110 sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers respectively connected to the plurality of planes. In other words, sensed data is transferred to page buffer within NVM 110 similar to second controller for buffer)
transfer, in response to the second command, the first portion of the data from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transfer, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface. (“the NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox (DO_PL1)”) (paragraph [0093], line 2-3)
(“NVM 110 may change the plane from which data is to be output from the first plane to the second plane and output the second page data loaded in a second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox (DO_PL2)”) (paragraph [0095], line 3-5) (i.e. NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox DO_PL1 and second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox DO_PL2. Examiner considers input/output bus is essentially an interface between NVM and controller)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 3, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 2. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 2, wherein, to transfer the second portion of the data from the second plane to the interface, the second controller is configured to cause the apparatus to:
transfer at least part of the second portion of the data from the second plane to the interface concurrent with the first portion of the data being transferred to the second controller
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The apparatus of claim 2, wherein, to transfer the second portion of the data from the second plane to the interface, the second controller is configured to cause the apparatus to:
transfer at least part of the second portion of the data from the second plane to the interface concurrent with the first portion of the data being transferred to the second controller. (“NVM 110 may, based on the read-out command set, simultaneously load page data stored in each of the at least two planes, for example, at least two portions of page data, into a sensing and page buffer and may continuously output the at least two page data, for example, the multi-plane page data DATA_MP, to the memory controller 120”) (paragraph [0095], line 3-5) (i.e. Fig 1 illustrates NVM 110 may based on the read-out command set simultaneously load page data stored in each of the at least two planes and may continuously output the multi-plane page data DATA_MP to the memory controller 120. In other words, transfer of data from two planes may output or transfer simultaneously or concurrently)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 3. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 3, wherein: the first portion of the data is transferred from the first plane to the interface via a first data path, and the second portion of the data is transferred from the second plane to the interface via a second data path
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The apparatus of claim 3, wherein: the first portion of the data is transferred from the first plane to the interface via a first data path, and the second portion of the data is transferred from the second plane to the interface via a second data path. (“the NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox (DO_PL1)”) (paragraph [0093], line 2-3)
(“NVM 110 may change the plane from which data is to be output from the first plane to the second plane and output the second page data loaded in a second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox (DO_PL2)”) (paragraph [0095], line 3-5) (i.e. NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox DO_PL1 and second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox DO_PL2. Examiner considers input/output bus is data path from NVM planes)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 1 is equally applicable to claim 4.
Regarding claim 7, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 1. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 1, wherein: the set of planes are organized into a sequence of planes, the command comprises an indication to automatically switch between the planes to transfer the portions of the data in accordance with the sequence, and
the second portion of the data is transferred to the second controller after the first portion of the data in accordance with the second plane being subsequent to the first plane in the sequence
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The apparatus of claim 1, wherein: the set of planes are organized into a sequence of planes, the command comprises an indication to automatically switch between the planes to transfer the portions of the data in accordance with the sequence, and (“The NVM 110 may output the page data of one plane selected based on the data output command set among the at least two page data stored in the at least two page buffers to the memory controller 120 and then switch planes and output the page data of the other plane to the memory controller 120”) (paragraph [0038], line 2-4) (i.e. Fig 1 illustrates NVM 110 may output the page data of one plane selected based on the data output command to the memory controller 120 and then switch planes to output the page data of the other plane to the memory controller)
the second portion of the data is transferred to the second controller after the first portion of the data in accordance with the second plane being subsequent to the first plane in the sequence. (“The multi-plane read command set may include addresses for each of the plurality of planes (e.g., a sequence of addresses of four planes) and a command representing a multi-plane read”) (paragraph [0047], line 3-5) (i.e. multi-plane read command may include addresses for each of the plurality of planes in a sequence of addresses of four planes. In other words, multi-plane read command has sequence of addresses of four planes to transfer data from NVM)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 1 is equally applicable to claim 7.
Regarding claim 8, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 7. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 7, wherein the indication to switch between the planes indicates a switch from a last column address of a current plane to a first column address of a next plane in the sequence
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The apparatus of claim 7, wherein the indication to switch between the planes indicates a switch from a last column address of a current plane to a first column address of a next plane in the sequence. (“The read confirm command RDC is a command indicating the end of the read sequence, that is, the end of a read command set, and may be, for example, 30h. The addresses of the first and second planes ADD_P1 and ADD_P2 may include a row address and a column address for the first and second planes, respectively”) (paragraph [0086], line 8-10) (i.e. Fig 7A illustrates read command set may have addresses of the first and second planes ADD_P1 and ADD_P2 which may include a row address and a column address for the first and second planes and also show end of read sequence. In other words, ADD_P1 and ADD_P2 may include full set of row and column address showing start and end address of each plane)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 10, Ahn teaches A non-transitory Computer readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: (“The host 200 may refer to a data processing device capable of processing data such as a Central Processing Unit (CPU), a processor, a microprocessor, an application processor), or the like”) (paragraph [0028], line 1-3) (i.e. Fig 1 illustrates host 200 may refer to a data processing device capable of processing data such as a Central Processing Unit (CPU) or a processor)
transfer, in response to issuing the command, a first portion of the data stored at a first plane of the set of planes to the second controller; and transfer, in response to issuing the command, a second portion of the data stored at a second plane of the set of planes to the second controller. (“The NVM 110 may transmit the plurality of portions of page data including the first page data to the memory controller 120 (S124). In this example, the first page data includes page data sensed from the first plane. Based on the data output command set, the NVM 110 may output the first page data of the first plane, and thereafter change the plane on which the page data is output to output page data of another plane. That is, the NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes”) (paragraph [0050], line 1-5) (i.e. Fig 2 step S124 illustrates NVM 110 110 may transmit or transfer the plurality of portions of page data including the first page data to the memory controller 120 and based on data output command set NVM 110 may output from first plane to another plane. In other words, NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes)
Ahn teaches memory device with multi plane data transfer. However, Ahn does not explicitly teach a command to transfer, in accordance with a sequence of the set of planes, portions of the data stored at respective planes of the set of planes to the second controller,
the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence,
On the other hand, Lu which also relates to memory device with multi plane data transfer teaches a command to transfer, in accordance with a sequence of the set of planes, portions of the data stored at respective planes of the set of planes to the second controller (see Fig 10 and 11, paragraph [0071] and [0108], illustrates commands for set of planes where portion data from different planes are sent to flash memory controller)
the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence (see Fig 10, paragraph [0108], illustrates address control circuit 1112 can control the row address decoder 1108 and column address decoder 1109 automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array)
automatically switch between the respective planes in accordance with the sequence (see Fig 13, paragraph [0115], illustrates automatic switching is done according to command sequence confirming address switching for multi plane)
Both Ahn and Lu relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and Lu, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn with Lu by incorporating memory device with multi plane data transfer in response to command from host, as taught by Lu, to enable automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array where switching is done according to command sequence confirming address switching for multi plane. The combined system of Ahn - Lu allows performing a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller as mentioned in paragraph [0005]. Therefore, the combination of Ahn - Lu improves performance of the flash memory device. See Lu, paragraph [0117].
Ahn in view of Lu and teaches memory device with multi plane data transfer. However, Ahn - Lu combination does not explicitly teach write, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes;
determine to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes;
issue, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written,
On the other hand, SHIN which also relates to memory device with multi plane data transfer teaches write, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes; (see Fig 1A and 2B, paragraph [0065], illustrates data is sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150)
determine to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes; (see Fig 2A and 2B, paragraph [0060], illustrates read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in any one of the memory devices 150 to 153)
issue, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written, the portions of the data stored at respective planes of the set of planes to the second controller; (see Fig 1A and 2B, paragraph [0065], illustrates read commands are sequentially generated or issued according to the order of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150 as they were written in sequence)
Both Ahn, Lu and SHIN relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and see Lu, abstract, and SHIN, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn - Lu combination with SHIN by incorporating memory device with multi plane data transfer in response to command from host, as taught by SHIN, to enable data to be sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device and read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 read commands are sequentially generated or issued according to the order of planes as they were written. The combined system of Ahn – Lu - SHIN allows a method which may include: performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, and storing the received data as mentioned in paragraph [0006]. Therefore, the combination of Ahn - Lu - SHIN improves operational reliability and communication performance. See SHIN, paragraph [0042].
Regarding claim 11, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 10. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: issue, to the first controller in response to the determination, a second command to sense the data
transfer, in response to the second command, the first portion of the data
from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transfer, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: issue, to the first controller in response to the determination, a second command to sense the data; (“The NVM 110 ma, sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers (at least two page buffers) respectively connected to the plurality of planes (S122) based on the multi-plane read command set”) (paragraph [0046], line 2-4) (i.e. Fig 2 step S122 illustrates after the command is transmitted in step S121, NVM 110 sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers respectively connected to the plurality of planes. In other words, sensed data is transferred to page buffer within NVM 110 similar to second controller for buffer)
transfer, in response to the second command, the first portion of the data
from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transfer, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface. (“the NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox (DO_PL1)”) (paragraph [0093], line 2-3)
(“NVM 110 may change the plane from which data is to be output from the first plane to the second plane and output the second page data loaded in a second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox (DO_PL2)”) (paragraph [0095], line 3-5) (i.e. NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox DO_PL1 and second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox DO_PL2. Examiner considers input/output bus is essentially an interface between NVM and controller)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 11.
Regarding claim 12, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 11. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 11, wherein the instructions to transfer the second portion of the data from the second plane to the interface, when executed by the processor of the electronic device, further cause the electronic device to:
transfer at least part of the second portion of the data from the second plane to the interface concurrent with the first portion of the data being transferred to the second controller
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 11, wherein the instructions to transfer the second portion of the data from the second plane to the interface, when executed by the processor of the electronic device, further cause the electronic device to:
transfer at least part of the second portion of the data from the second plane to the interface concurrent with the first portion of the data being transferred to the second controller. (“NVM 110 may, based on the read-out command set, simultaneously load page data stored in each of the at least two planes, for example, at least two portions of page data, into a sensing and page buffer and may continuously output the at least two page data, for example, the multi-plane page data DATA_MP, to the memory controller 120”) (paragraph [0095], line 3-5) (i.e. Fig 1 illustrates NVM 110 may based on the read-out command set simultaneously load page data stored in each of the at least two planes and may continuously output the multi-plane page data DATA_MP to the memory controller 120. In other words, transfer of data from two planes may output or transfer simultaneously or concurrently)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 12.
Regarding claim 13, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 12. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 12, wherein: the first portion of the data is transferred from the first plane to the interface via a first data path, and the second portion of the data is transferred from the second plane to the interface via a second data path
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 12, wherein: the first portion of the data is transferred from the first plane to the interface via a first data path, and the second portion of the data is transferred from the second plane to the interface via a second data path. (“the NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox (DO_PL1)”) (paragraph [0093], line 2-3)
(“NVM 110 may change the plane from which data is to be output from the first plane to the second plane and output the second page data loaded in a second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox (DO_PL2)”) (paragraph [0095], line 3-5) (i.e. NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox DO_PL1 and second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox DO_PL2. Examiner considers input/output bus is data path from NVM planes)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 13.
Regarding claim 16, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 10. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 10, wherein: the set of planes are organized into a sequence of planes, the command comprises an indication to automatically switch between the planes to transfer the portions of the data in accordance with the sequence, and
the second portion of the data is transferred to the second controller after the first portion of the data in accordance with the second plane being subsequent to the first plane in the sequence
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 10, wherein: the set of planes are organized into a sequence of planes, the command comprises an indication to automatically switch between the planes to transfer the portions of the data in accordance with the sequence, and (“The NVM 110 may output the page data of one plane selected based on the data output command set among the at least two page data stored in the at least two page buffers to the memory controller 120 and then switch planes and output the page data of the other plane to the memory controller 120”) (paragraph [0038], line 2-4) (i.e. Fig 1 illustrates NVM 110 may output the page data of one plane selected based on the data output command to the memory controller 120 and then switch planes to output the page data of the other plane to the memory controller)
the second portion of the data is transferred to the second controller after the first portion of the data in accordance with the second plane being subsequent to the first plane in the sequence. (“The multi-plane read command set may include addresses for each of the plurality of planes (e.g., a sequence of addresses of four planes) and a command representing a multi-plane read”) (paragraph [0047], line 3-5) (i.e. multi-plane read command may include addresses for each of the plurality of planes in a sequence of addresses of four planes. In other words, multi-plane read command has sequence of addresses of four planes to transfer data from NVM)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 16.
Regarding claim 17, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 16. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 16, wherein the indication to switch between the planes indicates a switch from a last column address of a current plane to a first column address of a next plane in the sequence
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 16, wherein the indication to switch between the planes indicates a switch from a last column address of a current plane to a first column address of a next plane in the sequence. (“The read confirm command RDC is a command indicating the end of the read sequence, that is, the end of a read command set, and may be, for example, 30h. The addresses of the first and second planes ADD_P1 and ADD_P2 may include a row address and a column address for the first and second planes, respectively”) (paragraph [0086], line 8-10) (i.e. Fig 7A illustrates read command set may have addresses of the first and second planes ADD_P1 and ADD_P2 which may include a row address and a column address for the first and second planes and also show end of read sequence. In other words, ADD_P1 and ADD_P2 may include full set of row and column address showing start and end address of each plane)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 17.
Regarding claim 18, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 16. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 16, wherein the command further comprises a bitmap that indicates one or more planes of the set of planes to exclude from the sequence as part of transferring the portions of the data to the second controller, and wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
refrain from transferring respective portions of the data stored at the one or
more planes to the second controller in accordance with the bitmap
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The non-transitory computer-readable medium of claim 16, wherein the command further comprises a bitmap that indicates one or more planes of the set of planes to exclude from the sequence as part of transferring the portions of the data to the second controller, and wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
refrain from transferring respective portions of the data stored at the one or
more planes to the second controller in accordance with the bitmap. (“In the Cache Read Data Transfer Phase 304, subsequent batches of multi-plane cache read commands may be issued with each batch followed by a respective set of data transfer commands. The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes. That is, based on the bitmaps, only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring”) (paragraph [0022], line 1-5) (i.e. Fig 3 illustrates Data Transfer Phase 304 where multi-plane cache read commands may be issued which may include data transfer and based on bitmap only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 10 is equally applicable to claim 18.
Regarding claim 19, Ahn teaches A method, comprising: determining, at a memory system, to read data stored across a set of planes of a non-volatile memory device of the memory system; issuing, to a first controller of the non-volatile memory device in response to the determination, a command to transfer portions of the data stored at respective planes of the set of planes to a second controller of the memory system; (“The memory controller 120 may transmit a multi-plane read command set to the NVM 110 (S121). The multi-plane read command set may instruct data sensing with respect to a plurality of planes (at least two planes) of the NVM 110”) (paragraph [0046], line 2-4) (i.e. Fig 2 step S121 illustrates memory controller 120 may transmit a multi-plane read command set to the NVM 110 and that read command may instruct data sensing with respect to a plurality of planes. In other words, memory controller 120 may transmit or issue a multi-plane read command to read or transfer data from plurality of planes)
transferring, in response to issuing the command, a first portion of the data stored at a first plane of the set of planes to the second controller; and transferring, in response to issuing the command, a second portion of the data stored at a second plane of the set of planes to the second controller. (“The NVM 110 may transmit the plurality of portions of page data including the first page data to the memory controller 120 (S124). In this example, the first page data includes page data sensed from the first plane. Based on the data output command set, the NVM 110 may output the first page data of the first plane, and thereafter change the plane on which the page data is output to output page data of another plane. That is, the NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes”) (paragraph [0050], line 1-5) (i.e. Fig 2 step S124 illustrates NVM 110 110 may transmit or transfer the plurality of portions of page data including the first page data to the memory controller 120 and based on data output command set NVM 110 may output from first plane to another plane. In other words, NVM 110 may change planes to output the plurality of portions of page data of the plurality of planes)
Ahn in view of Kuzmin teaches memory device with multi plane data transfer. However, Ahn – Kuzmin combination does not explicitly teach a command to transfer, in accordance with a sequence of the set of planes, portions of the data stored at respective planes of the set of planes to the second controller, the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence,
On the other hand, Lu which also relates to memory device with multi plane data transfer teaches
a command to transfer, in accordance with a sequence of the set of planes, portions of the data stored at respective planes of the set of planes to the second controller (see Fig 10 and 11, paragraph [0071] and [0108], illustrates commands for set of planes where portion data from different planes are sent to flash memory controller)
the command comprising an indication to automatically switch between respective planes of the set of planes to transfer the portions of the data in accordance with the sequence (see Fig 10, paragraph [0108], illustrates address control circuit 1112 can control the row address decoder 1108 and column address decoder 1109 automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array)
automatically switch between the respective planes in accordance with the sequence (see Fig 13, paragraph [0115], illustrates automatic switching is done according to command sequence confirming address switching for multi plane)
Both Ahn and Lu relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and Lu, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn with Lu by incorporating memory device with multi plane data transfer in response to command from host, as taught by Lu, to enable automatically switching to use the addresses of different planes based on only the address information so data corresponding to different planes can be transferred from memory array where switching is done according to command sequence confirming address switching for multi plane. The combined system of Ahn - Lu allows performing a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller as mentioned in paragraph [0005]. Therefore, the combination of Ahn - Lu improves performance of the flash memory device. See Lu, paragraph [0117].
Ahn in view of Lu and teaches memory device with multi plane data transfer. However, Ahn - Lu combination does not explicitly teach writing, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes;
Determining to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes;
issuing, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written,
On the other hand, SHIN which also relates to memory device with multi plane data transfer teaches writing, sequentially to a set of planes of the non-volatile memory device, data, wherein the data is written in accordance with a sequence of the set of planes; (see Fig 1A and 2B, paragraph [0065], illustrates data is sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150)
determining to read the data stored across the set of planes of the non- volatile memory device in accordance with an order corresponding to the sequence of the set of planes; (see Fig 2A and 2B, paragraph [0060], illustrates read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in any one of the memory devices 150 to 153)
issuing, to the first controller in response to the determination, a command to transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written, the portions of the data stored at respective planes of the set of planes to the second controller; (see Fig 1A and 2B, paragraph [0065], illustrates read commands are sequentially generated or issued according to the order of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150 as they were written in sequence)
Both Ahn, Lu and SHIN relate to the same field of endeavor, i.e., memory device with multi plane data transfer (see Ahn, abstract, and see Lu, abstract, and SHIN, abstract, regarding multi plane data transfer).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Ahn - Lu combination with SHIN by incorporating memory device with multi plane data transfer in response to command from host, as taught by SHIN, to enable data to be sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device and read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 read commands are sequentially generated or issued according to the order of planes as they were written. The combined system of Ahn – Lu - SHIN allows a method which may include: performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, and storing the received data as mentioned in paragraph [0006]. Therefore, the combination of Ahn - Lu - SHIN improves operational reliability and communication performance. See SHIN, paragraph [0042].
Regarding claim 20, Ahn in view of Lu and further in view of SHIN teaches memory device with multi plane data transfer in claim 19. However, Ahn - Lu - SHIN combination does not explicitly teach The method of claim 19, further comprising: issuing, to the first controller based at least in part on the determination, a second command to sense the data;
transferring, in response to the second command, the first portion of the data from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transferring, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface
On the other hand, Ahn which also relates to memory device with multi plane data transfer teaches The method of claim 19, further comprising: issuing, to the first controller based at least in part on the determination, a second command to sense the data; (“The NVM 110 ma, sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers (at least two page buffers) respectively connected to the plurality of planes (S122) based on the multi-plane read command set”) (paragraph [0046], line 2-4) (i.e. Fig 2 step S122 illustrates after the command is transmitted in step S121, NVM 110 sense page data from each of the plurality of planes and load the sensed page data in a plurality of page buffers respectively connected to the plurality of planes. In other words, sensed data is transferred to page buffer within NVM 110 similar to second controller for buffer)
transferring, in response to the second command, the first portion of the data from the first plane to an interface between the first plane and the second controller, wherein the first portion of the data is transferred to the second controller via the interface; and
transferring, in response to the second command, the second portion of the data from the second plane to the interface, wherein the second portion of the data is transferred to the second controller via the interface. (“the NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox (DO_PL1)”) (paragraph [0093], line 2-3)
(“NVM 110 may change the plane from which data is to be output from the first plane to the second plane and output the second page data loaded in a second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox (DO_PL2)”) (paragraph [0095], line 3-5) (i.e. NVM 110 may output the first page data to the memory controller 120 via the input/output bus I/Ox DO_PL1 and second page buffer of the second plane to the memory controller 120 via the input/output bus I/Ox DO_PL2. Examiner considers input/output bus is essentially an interface between NVM and controller)
The same motivation that was utilized for combining Ahn - Lu combination with SHIN as set forth in claim 19 is equally applicable to claim 20.
Claim(s) 5-6,9 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Lu and further in view of SHIN and further in view of Fu et al. (US 20240086317 A1) hereinafter Fu.
Regarding claim 5, Ahn in view of Lu and further in view of SHIN teaches multi plane data transfer in claim 1. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 1, wherein, to issue the command, the second controller is configured to cause the apparatus to: generate the command to include a bitmap that indicates chunks of the data comprising valid data and chunks of the data comprising invalid data,
wherein one or more chunks of the first portion of the data or one or more chunks of the second portion of the data indicated as comprising invalid data are excluded from being transferred to the second controller in accordance with the bitmap.
On the other hand, Fu which also relates to multi plane data transfer teaches The apparatus of claim 1, wherein, to issue the command, the second controller is configured to cause the apparatus to: generate the command to include a bitmap that indicates chunks of the data comprising valid data and chunks of the data comprising invalid data,
wherein one or more chunks of the first portion of the data or one or more chunks of the second portion of the data indicated as comprising invalid data are excluded from being transferred to the second controller in accordance with the bitmap. (“the storage controller 102 may generate bitmaps for valid data units in the blocks to be erased. For example, the storage controller 102 may obtain information that indicates which data units in a block contain valid data (referred to as valid data units), and which data units in a block have been marked as “bad” (no valid data)”) (paragraph [0017], line 5-8)
(“The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes”) (paragraph [0022], line 3-5) (i.e. Fig 3 illustrates storage controller 102 may generate bitmaps for valid data units where data units may be marked as valid or bad data and where data transfer commands may use this information to selectively identify valid data units for transferring from planes. In other words, bitmap is generated by storage controller to identify if data units or chunks are valid or not in order to transfer data chunks from planes)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Ahn - Lu combination with SHIN for the reasons set forth in claim 1 above. In addition, Ahn, Lu, SHIN and Fu are considered analogous arts,
because they all relate to the same field of endeavor, i.e., memory device multi plane data transfer. Ahn – Lu - SHIN combination teaches multi plane data transfer without any validity check. Ahn – Lu - SHIN combination does not teach data transfer bitmap indicating valid or invalid data for transferring data chunks from planes. On the other hand, Fu also teaches multi plane data transfer and data transfer bitmap indicating valid or invalid data for transferring data chunks from planes. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Ahn – Lu - SHIN combination with Fu to specify multi plane data transfer and data transfer bitmap indicating valid or invalid data for transferring data chunks from planes providing data transfer commands may include a last set of specified column addresses to selectively identify valid data units of a last page of data in the cache registers for transferring as mentioned in paragraph [0006].
Regarding claim 6, Ahn in view of Lu and further in view of SHIN teaches multi plane data transfer in claim 1. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 1, wherein, to issue the command, the second controller is configured to cause the apparatus to: generate the command to include a bitmap that indicates one or more planes of the set of planes to exclude as part of transferring the portions of the data to the second controller, wherein the second controller is further configured to cause the apparatus to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap.
On the other hand, Fu which also relates to multi plane data transfer teaches The apparatus of claim 1, wherein, to issue the command, the second controller is configured to cause the apparatus to: generate the command to include a bitmap that indicates one or more planes of the set of planes to exclude as part of transferring the portions of the data to the second controller, wherein the second controller is further configured to cause the apparatus to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap. (“In the Cache Read Data Transfer Phase 304, subsequent batches of multi-plane cache read commands may be issued with each batch followed by a respective set of data transfer commands. The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes. That is, based on the bitmaps, only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring”) (paragraph [0022], line 1-5) (i.e. Fig 3 illustrates Data Transfer Phase 304 where multi-plane cache read commands may be issued which may include data transfer and based on bitmap only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Ahn - Lu combination with SHIN for the reasons set forth in claim 1 above. In addition, Ahn, Lu, SHIN and Fu are considered analogous arts,
because they all relate to the same field of endeavor, i.e., memory device multi plane data transfer. Ahn – Lu - SHIN combination teaches multi plane data transfer without any validity check. Ahn – Lu - SHIN combination does not teach data transfer skipping or refraining for bitmap of valid and invalid data. On the other hand, Fu also teaches multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Ahn – Lu - SHIN combination with Fu to specify multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data providing data transfer commands may include a last set of specified column addresses to selectively identify valid data units of a last page of data in the cache registers for transferring as mentioned in paragraph [0006].
Regarding claim 9, Ahn in view of Lu and further in view of SHIN teaches multi plane data transfer in claim 7. However, Ahn - Lu - SHIN combination does not explicitly teach The apparatus of claim 7, wherein the command further comprises a bitmap that indicates one or more planes of the set of planes to exclude from the sequence as part of transferring the portions of the data to the second controller, and the second controller is further configured to cause the apparatus to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap.
On the other hand, Fu which also relates to multi plane data transfer teaches The apparatus of claim 7, wherein the command further comprises a bitmap that indicates one or more planes of the set of planes to exclude from the sequence as part of transferring the portions of the data to the second controller, and the second controller is further configured to cause the apparatus to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap. (“In the Cache Read Data Transfer Phase 304, subsequent batches of multi-plane cache read commands may be issued with each batch followed by a respective set of data transfer commands. The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes. That is, based on the bitmaps, only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring”) (paragraph [0022], line 1-5) (i.e. Fig 3 illustrates Data Transfer Phase 304 where multi-plane cache read commands may be issued which may include data transfer and based on bitmap only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Ahn - Lu combination with SHIN for the reasons set forth in claim 7 above. In addition, Ahn, Lu, SHIN and Fu are considered analogous arts,
because they all relate to the same field of endeavor, i.e., memory device multi plane data transfer. Ahn – Lu - SHIN combination teaches multi plane data transfer without any validity check. Ahn – Lu - SHIN combination does not teach data transfer skipping or refraining for bitmap of valid and invalid data. On the other hand, Fu also teaches multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Ahn – Lu - SHIN combination with Fu to specify multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data providing data transfer commands may include a last set of specified column addresses to selectively identify valid data units of a last page of data in the cache registers for transferring as mentioned in paragraph [0006].
Regarding claim 14, Ahn in view of Lu and further in view of SHIN teaches multi plane data transfer in claim 10. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory Computer readable medium of claim 10, wherein the instructions to issue the command, when executed by the processor of the electronic device, further cause the electronic device to:
generate the command to include a bitmap that indicates chunks of the data comprising valid data and chunks of the data comprising invalid data, wherein one or more chunks of the first portion of the data or one or more chunks of the second portion of the data indicated as comprising invalid data are excluded from being transferred to the second controller in accordance with the bitmap.
On the other hand, Fu which also relates to multi plane data transfer teaches The non-transitory Computer readable medium of claim 10, wherein the instructions to issue the command, when executed by the processor of the electronic device, further cause the electronic device to:
generate the command to include a bitmap that indicates chunks of the data comprising valid data and chunks of the data comprising invalid data, wherein one or more chunks of the first portion of the data or one or more chunks of the second portion of the data indicated as comprising invalid data are excluded from being transferred to the second controller in accordance with the bitmap. (“the storage controller 102 may generate bitmaps for valid data units in the blocks to be erased. For example, the storage controller 102 may obtain information that indicates which data units in a block contain valid data (referred to as valid data units), and which data units in a block have been marked as “bad” (no valid data)”) (paragraph [0017], line 5-8)
(“The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes”) (paragraph [0022], line 3-5) (i.e. Fig 3 illustrates storage controller 102 may generate bitmaps for valid data units where data units may be marked as valid or bad data and where data transfer commands may use this information to selectively identify valid data units for transferring from planes. In other words, bitmap is generated by storage controller to identify if data units or chunks are valid or not in order to transfer data chunks from planes)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Ahn - Lu combination with SHIN for the reasons set forth in claim 10 above. In addition, Ahn, Lu, SHIN and Fu are considered analogous arts,
because they all relate to the same field of endeavor, i.e., memory device multi plane data transfer. Ahn – Lu - SHIN combination teaches multi plane data transfer without any validity check. Ahn – Lu - SHIN combination does not teach data transfer bitmap indicating valid or invalid data for transferring data chunks from planes. On the other hand, Fu also teaches multi plane data transfer and data transfer bitmap indicating valid or invalid data for transferring data chunks from planes. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Ahn – Lu - SHIN combination with Fu to specify multi plane data transfer and data transfer bitmap indicating valid or invalid data for transferring data chunks from planes providing data transfer commands may include a last set of specified column addresses to selectively identify valid data units of a last page of data in the cache registers for transferring as mentioned in paragraph [0006].
Regarding claim 15, Ahn in view of Lu and further in view of SHIN teaches multi plane data transfer in claim 10. However, Ahn - Lu - SHIN combination does not explicitly teach The non-transitory computer-readable medium of claim 10, wherein the instructions to issue the command, when executed by the processor of the electronic device, further cause the electronic device to: generate the command to include a bitmap that indicates one or more planes of the set of planes to exclude as part of transferring the portions of the data to the second controller, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap.
On the other hand, Fu which also relates to multi plane data transfer teaches The non-transitory computer-readable medium of claim 10, wherein the instructions to issue the command, when executed by the processor of the electronic device, further cause the electronic device to: generate the command to include a bitmap that indicates one or more planes of the set of planes to exclude as part of transferring the portions of the data to the second controller, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
refrain from transferring respective portions of the data stored at the one or more planes to the second controller in accordance with the bitmap. (“In the Cache Read Data Transfer Phase 304, subsequent batches of multi-plane cache read commands may be issued with each batch followed by a respective set of data transfer commands. The data transfer commands may include specified column addresses to selectively identify valid data units of the page of data in the cache registers for transferring from the planes. That is, based on the bitmaps, only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring”) (paragraph [0022], line 1-5) (i.e. Fig 3 illustrates Data Transfer Phase 304 where multi-plane cache read commands may be issued which may include data transfer and based on bitmap only data units containing valid data units may be selected to be transferred out of the NAND device and other data units may be skipped for transferring)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Ahn - Lu combination with SHIN for the reasons set forth in claim 10 above. In addition, Ahn, Lu, SHIN and Fu are considered analogous arts,
because they all relate to the same field of endeavor, i.e., memory device multi plane data transfer. Ahn – Lu - SHIN combination teaches multi plane data transfer without any validity check. Ahn – Lu - SHIN combination does not teach data transfer skipping or refraining for bitmap of valid and invalid data. On the other hand, Fu also teaches multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Ahn – Lu - SHIN combination with Fu to specify multi plane data transfer and data transfer skipping or refraining for bitmap of valid and invalid data providing data transfer commands may include a last set of specified column addresses to selectively identify valid data units of a last page of data in the cache registers for transferring as mentioned in paragraph [0006].
Response to Arguments
Applicant’s arguments filed on 02/20/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1,10 and 19 amendments mapping by
primary and secondary references in page 10 of the response: Without conceding the merits of the rejection of independent claims 1, 10, and 19 under 35 U.S.C. § 103-and solely to expedite prosecution-Applicant has amended independent claims 1, 10, and 19. For example, independent claim 1 has been amended to recite:
write, sequentially to a set of planes of the non-volatile memory device,
data, wherein the data is written in accordance with a sequence of the set of
planes;
determine to read the data stored across the set of planes of the non-volatile
memory device in accordance with an order corresponding to the sequence of the
set of planes;
issue, to the first controller in response to the determination, a command to
transfer, in accordance with the order of the sequence of the set of planes in which portions of the data were written, the portions of the data stored at respective planes of the set of planes to the second controller, the command comprising an indication to automatically switch between the respective planes of the set of planes to transfer the portions of the data in accordance with the
sequence;
transfer, in response to issuing the command and in accordance with the
sequence, a first portion of the data stored at a first plane of the set of planes to the
second controller; and
transfer, in response to issuing the command and in accordance with the
indication to automatically switch between the respective planes in accordance with the sequence, a second portion of the data stored at a second plane of the set of
planes to the second controller.
Ahn, Kuzmin, Lu, and Fu-alone or in any combination-do not teach or suggest all of the features of amended independent claims 1, 10, and 19
In summary, applicant argued that primary reference Ahn and secondary references Kuzmin and Lu do not teach amended limitations of independent claims writing sequentially to a set of planes in accordance to sequence of planes and transfer commands with the order of sequence of planes. The amendment necessitates adding secondary reference SHIN in this regard. For further clarification examiner cites
portion from SHIN. Also, for applicant’s understanding examiner would like to explain
the teachings of SHIN and examiner’s interpretation in more detail here. See Fig 1A and 2B, paragraph [0065], SHIN teaches data is sequentially stored or written in the four planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150. Also see Fig 2A and 2B, paragraph [0060], SHIN teaches read operations are sequentially performed on the sequence of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in any one of the memory devices 150 to 153 and see Fig 1A and 2B, paragraph [0065], SHIN teaches read commands are sequentially generated or issued according to the order of planes PLANE0, PLANE1, PLANE2, and PLANE3 that are included in the memory device 150 as they were written in sequence. The cited portion along with Fig 1, 2A and 2B clearly teaches writing and reading operations are performed in accordance to sequence of the planes of memory device and also read commands are sequentially generated or issued according to the order of planes. Thus, the rejection of amended claims 1,10 and 19 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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