DETAILED ACTION
This Office Action, based on application 18/542,538 filed 15 December 2023, is filed in response to applicant’s amendment and remarks filed 24 November 2025. Claims 1-20 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, submitted 24 November 2025 in response to the Office Action mailed 27 August 2025, have been fully considered below.
Claim Objections
The Office withdraws the previously issued objections in view of applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection to the claims alleging cited prior art fails to teach or disclose applicant’s claimed invention as amended. The applicant has further amended the independent claims to characterize a ‘fake block’ as follows:
the fake block is a memory block in which actual data used for a test is not written
the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written
In response, the Office asserts the limitations above do not significantly limit the claim or limit the claim as intended by the applicant given the broadest reasonable interpretation of the claim. Any block of the plurality of memory blocks may be considered to be a ‘fake block’ given that the block is identified in some manner in a bitmap. Furthermore, the first limitation merely states that ‘actual data’ used in a test isn’t written to the ‘fake block’ and the second limitation merely states that ‘actual data’ is written to a ‘normal block’. The limitations merely establish that some data used in a test is written to the normal block and that data isn’t also stored in the ‘fake block’. The limitations do not prohibit other data (that is not ‘actual data’) from being written to the ‘fake block’ even during a test. For example, if ‘actual data’ is the string “123”, then writing “123” to the ‘normal block’ meets the broadest reasonable interpretation of the limitation. Furthermore, writing the string “xyz” to the ‘fake block’, even during the test, does not infringe on the limitation since “xyz” is not ‘actual data’ (e.g. the string “123”) written to the ‘normal block’. The Office maintains a prior art rejection to the claims as the Office asserts cited prior art meets the broadest reasonable interpretation of the claims for reasons now presented below.
Claim Objections
The following claims are objected to due to informalities:
Claims 1, 17, and 18: The word ‘the’ should be inserted in the limitation “wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which the actual data is written” in order to properly reflect antecedent basis of the term ‘actual data’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOLAN et al (US PGPub 2021/0248050) in further view of PARKER et al (US PGPub 2023/0205709) and SINCLAIR (US PGPub 2007/0033325).
With respect to Claim 1, KOLAN discloses a storage device comprising:
a nonvolatile memory including a plurality of memory blocks (Fig 2, Memory 207; ¶[0041] – “assuming each access does not exceed 512 memory blocks”); and
a controller configured to control an operation of the nonvolatile memory (Fig 2, Processor(s) 202; ¶[0015-0016] – “the target processor may be configured to utilize different address translation tables in different contexts … During execution of a process, whenever a memory is accessed using a virtual address, the virtual address may be translated into a physical address”), generate a mapping table that maps physical addresses and logical addresses for the plurality of memory blocks in a test mode (¶[0044] – “a first translation table may be determined. The first translation table may define a first mapping from a first set of virtual address{es} to a first set of physical addresses. … the first translation table may be embedded … to be utilized during the generation of tests based thereon”).
KOLAN may not explicitly disclose a controller to set a fake block bitmap indicating a block from the plurality of memory blocks included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, wherein the fake block according to the mapping table is recognized as having written data, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written.
However, PARKER discloses a controller to set a fake block bitmap indicating a block from the plurality of memory blocks included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written (¶[0050] – “defining variable sized offset portions for a given level based on the variable nesting control parameter in the higher-level access control table can also be applied to page tables or any other access control table structure {e.g. ‘fake block bitmap’} indexed by virtual address. The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses is readable/writable or limiting which privilege/exception levels are allowed to access the region”. The Office asserts setting a first region using some combination of privilege or exception level or access permission {e.g. not readable or supervisor-only privilege level} in the access control table structure as being analogous to indicating a ’fake block’ and writing particular data during a test to a second region with a different combination of privilege or exception level or access permissions analogous to writing to a ‘normal block’.).
KOLAN and PARKER are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN and PARKER before him or her, to modify the address translation table of KOLAN to include access control information as taught by PARKER. A motivation for doing so would have been to enable access control of a virtual address space to protect corresponding physical addresses from unauthorized access or corruption. Therefore, it would have been obvious to combine KOLAN and PARKER to obtain the invention as specified in the instant claims.
KOLAN and PARKER may not explicitly disclose wherein the fake block according to the mapping table is recognized as having written data.
However, SINCLAIR discloses wherein the fake block according to the mapping table is recognized as having written data (¶[0055] – “The overhead portion 159 may contain … an experience count of the number of times the block has been erased and re-programmed … Alternatively, the overhead data 159, or a portion of it, may be stored in different pages in other blocks”).
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection and experience count tracking as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 17, KOLAN discloses a method for setting a test mode of a storage device, comprising:
mapping an arbitrary physical address to a logical address in a test mode; generating a mapping table that maps the physical address and the logical address using a mapping relationship (¶[0044] – “a first translation table may be determined. The first translation table may define a first mapping from a first set of virtual address{es} to a first set of physical addresses. … the first translation table may be embedded … to be utilized during the generation of tests based thereon”).
KOLAN may not explicitly disclose setting a fake block bitmap indicating whether a memory block included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, wherein the fake block according to the mapping table is recognized as having written data, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written.
However, PARKER discloses setting a fake block bitmap indicating whether a memory block included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written (¶[0050] – “defining variable sized offset portions for a given level based on the variable nesting control parameter in the higher-level access control table can also be applied to page tables or any other access control table structure {e.g. ‘fake block bitmap’} indexed by virtual address. The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses is readable/writable or limiting which privilege/exception levels are allowed to access the region”. The Office asserts setting a first region using some combination of privilege or exception level or access permission {e.g. not readable or supervisor-only privilege level} in the access control table structure as being analogous to indicating a ’fake block’ and writing particular data during a test to a second region with a different combination of privilege or exception level or access permissions analogous to writing to a ‘normal block’.).
KOLAN and PARKER are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN and PARKER before him or her, to modify the address translation table of KOLAN to include access control information as taught by PARKER. A motivation for doing so would have been to enable access control of a virtual address space to protect corresponding physical addresses from unauthorized access or corruption. Therefore, it would have been obvious to combine KOLAN and PARKER to obtain the invention as specified in the instant claims.
KOLAN and PARKER may not explicitly disclose wherein the fake block according to the mapping table is recognized as having written data.
However, SINCLAIR discloses wherein the fake block according to the mapping table is recognized as having written data (¶[0055] – “The overhead portion 159 may contain … an experience count of the number of times the block has been erased and re-programmed … Alternatively, the overhead data 159, or a portion of it, may be stored in different pages in other blocks”).
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection and experience count tracking as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 18, KOLAN discloses a controller comprising:
an interface configured to receive a test mode start signal from an outside (¶[0036] – “a test template may be obtained. The test template may comprise a set of directives. In some exemplary embodiments, the test template may be defined by a verification engineer {analogous to ‘from the outside’}”); and
a control circuit configured to operate in a test mode according to the test mode start signal, generate a mapping table between physical addresses and logical addresses according to a plurality of memory blocks in the test mode (¶[0044] – “a first translation table may be determined. The first translation table may define a first mapping from a first set of virtual address{es} to a first set of physical addresses. … the first translation table may be embedded … to be utilized during the generation of tests based thereon”; Fig 1A, Step 124 – “Determine a first translation table” happens subsequent to Step 110 – “Obtain a test template”).
KOLAN may not explicitly disclose a control circuit configured to set a fake block bitmap indicating whether the memory block included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, wherein the fake block according to the mapping table is recognized as having written data, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written.
However, PARKER discloses a control circuit configured to set a fake block bitmap indicating whether the memory block included in the mapping table is a fake block, wherein the fake block is a memory block in which actual data used for a test is not written, and wherein the fake block is distinguished from a normal block in the plurality of memory blocks in which actual data is written. (¶[0050] – “defining variable sized offset portions for a given level based on the variable nesting control parameter in the higher-level access control table can also be applied to page tables or any other access control table structure {e.g. ‘fake block bitmap’} indexed by virtual address. The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses is readable/writable or limiting which privilege/exception levels are allowed to access the region”. The Office asserts setting a first region using some combination of privilege or exception level or access permission {e.g. not readable or supervisor-only privilege level} in the access control table structure as being analogous to indicating a ’fake block’ and writing particular data during a test to a second region with a different combination of privilege or exception level or access permissions analogous to writing to a ‘normal block’.).
KOLAN and PARKER are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN and PARKER before him or her, to modify the address translation table of KOLAN to include access control information as taught by PARKER. A motivation for doing so would have been to enable access control of a virtual address space to protect corresponding physical addresses from unauthorized access or corruption. Therefore, it would have been obvious to combine KOLAN and PARKER to obtain the invention as specified in the instant claims.
KOLAN and PARKER may not explicitly disclose wherein the fake block according to the mapping table is recognized as having written data.
However, SINCLAIR discloses wherein the fake block according to the mapping table is recognized as having written data (¶[0055] – “The overhead portion 159 may contain … an experience count of the number of times the block has been erased and re-programmed … Alternatively, the overhead data 159, or a portion of it, may be stored in different pages in other blocks”).
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection and experience count tracking as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN further discloses wherein the controller maps an arbitrary physical address from among a plurality of physical addresses to each of the logical addresses, and generates the mapping table using a mapping relationship between the logical address and the physical address (¶[0044] – “a first translation table may be determined. The first translation table may define a first mapping from a first set of virtual address{es} to a first set of physical addresses. … the first translation table may be embedded … to be utilized during the generation of tests based thereon”).
With respect to Claim 3, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN further discloses wherein the controller generates the mapping table without receiving a write command from an outside of the storage device (Fig 1 illustrates Step 124 – “Determine a first translation table” is performed subsequent to Step 110 – “Obtain a test template” {analogous to ‘without receiving a write command from the outside of the storage device’}).
With respect to Claim 4, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN, PARKER, and SINCLAIR may not explicitly disclose wherein the controller sets all of the plurality of memory blocks as fake blocks, except at least one of the plurality of memory blocks set as an over-provision region.
However, PARKER states ¶[0047] that “in a system in which a virtual address of a memory access request can be mapped to a physical address in one of two or more distinct physical address spaces, granule protection information can be used to limit which physical addresses are accessible within a particular physical address space”; the Abstract states “Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address”; and ¶[0050] states “The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses is readable/writable or should be read-only, or limiting which privilege/exception levels are allowed to access the region.” which at least suggests the access control information may be applied to any memory block such that any particular block may be access limited as being readable/writable {analogous to ‘normal’} or read-only {analogous to ‘fake’}.
As such, with the suggestions asserted by PARKER, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration KOLAN, PARKER, and SINCLAIR’s explicit teachings and suggestions to have been able to modify the combination of KOLAN, PARKER, and SINCLAIR such that the controller sets all of the memory blocks, except a memory block set as an over-provision region among the plurality of memory blocks, as fake blocks with a reasonable expectation of success.
A motivation for doing so would be to enable write testing to the over-provisioning region of a memory while protecting the contents of the other regions for memory testing.
With respect to Claim 5, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN, PARKER, and SINCLAIR may not explicitly disclose wherein the controller sets some of the plurality of memory blocks as fake blocks, sets at least one of the plurality of memory blocks as an over-provision region and sets a remainder of the plurality of memory blocks as normal blocks.
However, PARKER states ¶[0047] that “in a system in which a virtual address of a memory access request can be mapped to a physical address in one of two or more distinct physical address spaces, granule protection information can be used to limit which physical addresses are accessible within a particular physical address space”; the Abstract states “Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address”; and ¶[0050] states “The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses is readable/writable or should be read-only, or limiting which privilege/exception levels are allowed to access the region.” which at least suggests the access control information may be applied to any memory block such that any particular block may be access limited as being readable/writable {analogous to ‘normal’} or read-only {analogous to ‘fake’}.
As such, with the suggestions asserted by PARKER, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration KOLAN, PARKER, and SINCLAIR’s explicit teachings and suggestions to have been able to modify the combination of KOLAN, PARKER, and SINCLAIR such that the controller sets some of the memory blocks, except a memory block set as an over-provision region from among the plurality of memory blocks, as fake blocks, and sets remaining memory blocks, except the memory blocks set as the fake blocks and the memory block set as the over-provision region, as normal blocks.
A motivation for doing so would be to enable write testing to the over-provisioning region of a memory and another specific region of memory while protecting the contents of the other regions for memory testing.
With respect to Claim 6, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
PARKER further discloses wherein, when receiving a read command for a fake block from an outside, the controller outputs information on the fake block stored in the mapping table (Fig 10, Step 170 – “Filter receives memory access request …” => Step 172 – “Obtain GPI” {granule protection information} => ‘Y’ => Step 176 – “Allow memory access request …”).
With respect to Claim 7, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN and PARKER may not explicitly disclose wherein, when receiving a write command for a fake block from an outside, the controller changes the physical address for the fake block to another physical address in the mapping table, and writes data according to the write command to the memory block corresponding to the changed physical address.
However, SINCLAIR discloses wherein, when receiving a write command for a fake block from an outside, the controller changes the physical address for the fake block to another physical address in the mapping table, and writes data according to the write command to the memory block corresponding to the changed physical address (¶[0068] – “During garbage collection, pages of valid data with contiguous or near contiguous logical address ranges are gathered from one or more source blocks containing obsolete data and re-written into a destination block”)
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 8, the combination of KOLAN and PARKER disclose the storage device according to claim 1.
KOLAN and PARKER may not explicitly disclose wherein, when a number of free blocks among the plurality of memory blocks is less than a preset value, the controller performs a garbage collection operation, after the garbage collection operation, the number of free blocks excludes the fake block.
However, SINCLAIR discloses wherein, when a number of free blocks among the plurality of memory blocks is less than a preset value, the controller performs a garbage collection operation, after the garbage collection operation, the number of free blocks excludes the fake block (¶[0080] – “The trigger for beginning such interleaved garbage collection may be that the number of erased blocks reaches some threshold” {‘erased blocks’ are analogous to ‘free blocks’ and not ‘fake blocks’}).
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 9, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 8.
SINCLAIR further discloses wherein, when performing the garbage collection operation, the controller selects the fake block as a source block from among the plurality of memory blocks (¶[0068] – “During garbage collection, pages of valid data with contiguous or near contiguous logical address ranges are gathered from one or more source blocks containing obsolete data and re-written into a destination block”).
With respect to Claim 10, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 9.
SINCLAIR further discloses wherein the controller writes a value obtained in a read operation on the source block, to a destination block to which data of the source block is to be moved (¶[0068] – “During garbage collection, pages of valid data with contiguous or near contiguous logical address ranges are gathered from one or more source blocks containing obsolete data and re-written into a destination block”).
With respect to Claim 11, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 9.
SINCLAIR further discloses wherein the controller sets a destination block, to which the data of the source block is moved, as a fake block, and changes the source block to a normal block, in the fake block bitmap (¶[0065] – “Data stored at specific host logical addresses are frequently replaced by new data as the original stored data become obsolete. The memory system controller, in response, writes the new data in an erased block and then changes the logical-to-physical address table for those logical addresses to identify the new physical block to which the data at those logical addresses are stored. The blocks containing the original data at those logical addresses are then erased and made available for the storage of new data.”).
With respect to Claim 12, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 9.
SINCLAIR further discloses wherein, when the garbage collection operation is completed, the controller changes the source block to a normal block in the fake block bitmap (¶[0065] – “Data stored at specific host logical addresses are frequently replaced by new data as the original stored data become obsolete. The memory system controller, in response, writes the new data in an erased block and then changes the logical-to-physical address table for those logical addresses to identify the new physical block to which the data at those logical addresses are stored. The blocks containing the original data at those logical addresses are then erased and made available for the storage of new data.”).
With respect to Claim 13, the combination of KOLAN and PARKER disclose the storage device according to claim 5.
KOLAN and PARKER may not explicitly disclose wherein, when a number of free blocks from among the plurality of memory blocks is less than a preset value, the controller performs a garbage collection operation, and the fake blocks are excluded from the number of free blocks, wherein, when performing the garbage collection operation, the controller selects, as a source block, a memory block written with data from among the normal blocks.
However, SINCLAIR discloses wherein, when a number of free blocks from among the plurality of memory blocks is less than a preset value, the controller performs a garbage collection operation, and the fake blocks are excluded from the number of free blocks (¶[0080] – “The trigger for beginning such interleaved garbage collection may be that the number of erased blocks reaches some threshold” {‘erased blocks’ are analogous to ‘free blocks’ and not ‘fake blocks’}), wherein, when performing the garbage collection operation, the controller selects, as a source block, a memory block written with data from among the normal blocks (¶[0068] – “During garbage collection, pages of valid data with contiguous or near contiguous logical address ranges are gathered from one or more source blocks containing obsolete data and re-written into a destination block”).
KOLAN, PARKER, and SINCLAIR are analogous art because they are from the same field of endeavor of management of memory address translation. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOLAN, PARKER, and SINCLAIR before him or her, to modify the execution of the apparatus of the combination of KOLAN and PARKER to include garbage collection as taught by SINCLAIR. A motivation for doing so would have been to prevent the number of erased blocks to be diminished to a point where host data can no longer be written thus reducing the risk of host timeout or aborting of programming (¶[0080]). Therefore, it would have been obvious to combine KOLAN, PARKER, and SINCLAIR to obtain the invention as specified in the instant claims.
With respect to Claim 14, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
PARKER further discloses a volatile memory configured to store the mapping table and the fake block bitmap (¶[0084] – “The GPT 56 can reside in on-chip SRAM or in off-chip DRAM”).
With respect to Claim 15, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
PARKER further discloses wherein at least two of the plurality of memory blocks configure a super block, and the fake block bitmap indicates whether the super block is a fake block (¶[0050] - “The access control information discussed above could comprise the addressing mapping information from the page tables used for address translation, and could also comprise other access permission information defined in the page tables, such as information defining whether a region of virtual addresses {analogous to a ‘superblock’} is readable/writable or should be read-only, or limiting which privilege/exception levels are allowed to access the region.”).
With respect to Claim 16, the combination of KOLAN, PARKER, and SINCLAIR disclose the storage device according to claim 1.
KOLAN further discloses wherein the test mode is enabled according to a test mode start signal received from an outside (¶[0036] – “a test template may be obtained. The test template may comprise a set of directives. In some exemplary embodiments, the test template may be defined by a verification engineer {analogous to ‘from the outside’}”).
With respect to Claim 19, the combination of KOLAN, PARKER, and SINCLAIR disclose the controller according to claim 18.
PARKER further discloses a volatile memory configured to store the fake block bitmap (¶[0084] – “The GPT 56 can reside in on-chip SRAM or in off-chip DRAM”).
With respect to Claim 20, the combination of KOLAN, PARKER, and SINCLAIR disclose the controller according to claim 18.
PARKER further discloses wherein the fake block bitmap is stored in a memory located outside the controller (¶[0084] – “The GPT 56 can reside in on-chip SRAM or in off-chip DRAM”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T LOONAN/Examiner, Art Unit 2137
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