Prosecution Insights
Last updated: October 04, 2026
Application No. 18/542,593

ENCAPSULATION STRUCTURE FOR MEMORY DEVICES

Non-Final OA §102§103§112
Filed
Dec 16, 2023
Examiner
HSIEH, HSIN YI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kepler Computing Inc.
OA Round
1 (Non-Final)
51%
Grant Probability
Moderate
1-2
OA Rounds
1y 1m
Est. Remaining
57%
With Interview

Examiner Intelligence

Grants 51% of resolved cases
51%
Career Allowance Rate
326 granted / 641 resolved
-17.1% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
31 currently pending
Career history
698
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.2%
-2.8% vs TC avg
§102
20.2%
-19.8% vs TC avg
§112
40.6%
+0.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 641 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I and Species 1 of Fig. 1A in the reply filed on 07/14/2026 is acknowledged. The traversal on the election of Inventions is on the ground(s) that Invention Group III requires all of the structural limitations of the capacitor structure recited in Invention Group I, and Claim 15 of Invention Group II recites substantially the same capacitor structure as Claim 1, merely in a plurality configuration, and there would be no serious search and/or examination burden if restriction were not required. The traversal on the election of Species is on the ground(s) that the species are obvious variants of each other, the core structure common to all species is the same, the differences between species represent routine design choices in semiconductor fabrication. This is not found persuasive because, firstly, regarding the election of Invention Group I, Invention Group III and Invention Group II do not require some particulars of claim 1 as explicitly disclosed in the Restriction Requirement mailed on 05/14/2026 and Invention Groups I-III belong to different classifications which would place serious search and/or examination burden on the examiner. Secondly, regarding the election of Species, all the Species listed in the Restriction Requirement mailed on 05/14/2026 have distinct features which make them not the obvious variants from each other. All these features are explicitly shown in the Restriction Requirement mailed on 05/14/2026. It does not matter whether these distinct features are the common cores structures or they are the products of routine design choices. These distinct features would require a different field of search, i.e. employing different search strategies or search queries due to their structural differences, which would place serious search and/or examination burden on the examiner. The requirement is still deemed proper and is therefore made FINAL. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/14/2026. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recited the limitation “wherein the second portion is in contact with the insulator”, which is inconstant with the elected species 1 of Fig. 1A. Fig. 1A shows that the second portion 114B is not in contact with the insulator 118. The inconsistency renders the claim indefinite. Claims 9-12 are rejected because they depend on the rejected claim 8. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 5, 8-9, 11-14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Mathuriya et al. (US 2023/0223936 A1). Regarding claim 1, Mathuriya et al. teach a device structure (the capacitor circuit 1600 of Fig. 16A with the planar capacitor of 1823b of Fig. 18B; [0179, 0190]) comprising: an electrode structure (pedestal in contact with C1; Fig. 16A, [0180-0181]); a capacitor structure (C1; Fig. 16A; [0181]) on the electrode structure (pedestal in contact with C1; Fig. 16A), the capacitor structure (C1 in Fig. 16A, i.e. 1823b in Fig. 18B; [0181, 0190]) comprising: a bottom electrode structure (1812b/1811b/bottom electrode of 1823b; Fig. 4B, [0192, 0191, 0189]) comprising: a first electrode (bottom electrode of 1823b; Fig. 18B, [0189]) comprising a first lateral thickness (the lateral thickness of bottom electrode of 1823b); and a second electrode (1811b of 1823b; Fig. 18B, [0191]) on the first electrode (bottom electrode of 1823b), the second electrode (1811b of 1823b) comprising a second lateral thickness (the lateral thickness of 1811b of 1823b) greater than the first lateral thickness (the lateral thickness of bottom electrode of 1823b; see Fig. 18B); a dielectric (1813 of 1823b; Fig. 18B, [0144]) comprising a non-linear polar material ([0039]) having a form ABB'O3, AA'B'O3, or ABO3, wherein A' is a first dopant for atomic site A, wherein B' is a second dopant for atomic site B, and wherein O is oxygen (BiFeO3, ferroelectric, i.e. nonlinear polar material, in the form of ABO3 with A=Bi, B=Fe; [0052], [0039]); and a third electrode (top electrode or 1811a of 1823b; Fig. 18B, [0189, 0191]) on the dielectric (1813 of 1823b; Fig. 18B); and an encapsulation structure (1821a-1821f of 1823b; Fig. 18B, [0191-0192]) comprising: a first portion (1821e and a portion of 1821a in contact with 1811b of 1823b; Fig. 18B, [0192]) adjacent to a first sidewall of the first electrode (the left sidewall of the bottom electrode of 1823b) and adjacent to a lower surface of the second electrode (the bottom surface of 1811b of 1823b); and a second portion (the upper portion of 1821a above the top surface of 1811b of 1823b; Fig. 18B, [0191]) adjacent to a second sidewall of the second electrode (the left sidewall of 1811b of 1823b), a third sidewall of the dielectric (the left sidewall of 1813 of 1823b), and a fourth sidewall of the third electrode (the left sidewall of the top electrode or 1811a of 1823b). Regarding claim 5, Mathuriya et al. teach the device structure of claim 1, wherein the first electrode (bottom electrode of 1823b) has a vertical thickness (the vertical thickness of the bottom electrode of 1823b) orthogonal to the first lateral thickness (the lateral thickness of bottom electrode of 1823b), wherein the first portion (1821e and a portion of 1821a in contact with 1811b of 1823b) has a fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b), and wherein the fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b) is different from the vertical thickness (the vertical thickness of the bottom electrode of 1823b, implied in Fig. 18B). Regarding claim 8, Mathuriya et al. teach the device structure of claim 1, further comprising an insulator (ILD; Fig. 16A, [0180]) laterally adjacent to the electrode structure (pedestal in contact with C1; see Fig. 16A), wherein the second portion (the upper portion of 1821a above the top surface of 1811b of 1823b) is in contact with the insulator (Fig. 16A shows ILD in contact with the external side surfaces of the capacitor C1 and Fig. 18B shows the external side surfaces of the upper portion of 1821a above the top surface of 1811b of 1823b are the external side surfaces of the capacitor). Regarding claim 9, Mathuriya et al. teach the device structure of claim 8, further comprising a liner (etch stop layer in contact with the pedestal in contact with C1, Fig. 16A, [0179]) between the insulator (ILD) and the electrode structure (pedestal in contact with C1; see Fig. 16A), wherein the second portion (the upper portion of 1821a above the top surface of 1811b of 1823b) further extends on the liner (etch stop layer in contact with the pedestal in contact with C1, Fig. 16A; see Figs. 16A and Fig. 18B). Regarding claim 11, Mathuriya et al. teach the device structure of claim 8, wherein the encapsulation structure (1821a-1821f of 1823b) further comprising a third portion (1821c; Fig. 18B, [0191-0192]) that extends laterally on the insulator (ILD; see Fig. 16A) beyond an outer sidewall of the second portion (the right sidewall of the upper portion of 1821a above the top surface of 1811b of 1823b). Regarding claim 12, Mathuriya et al. teach the device structure of claim 11, wherein the encapsulation structure (1821a-1821f of 1823b) further comprising a fourth portion (1821c; Fig. 18B, [0191-0192]) that extends on the second portion (the upper portion of 1821a above the top surface of 1811b of 1823b) and on an uppermost surface of the third electrode (1811a of 1823b). Regarding claim 13, Mathuriya et al. teach the device structure of claim 5, wherein the second portion (the upper portion of 1821a above the top surface of 1811b of 1823b) comprises a fifth lateral thickness (the lateral thickness of the upper portion of 1821a above the top surface of 1811b of 1823b), and wherein a minimum value of the fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b) is equal to the fifth lateral thickness (the lateral thickness of the upper portion of 1821a above the top surface of 1811b of 1823b; see Fig. 18B). Regarding claim 14, Mathuriya et al. teach the device structure of claim 1, wherein the dielectric (1813 of 1823b) comprises: the form ABB'O3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein B' includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn; the form ABO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein B includes one of Mn, Fe, Ta, or Nb; or the form AA'BO3, wherein A includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein B includes one of Mn, Fe, Ta, or Nb, and wherein A' includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, or Lu (BiFeO3, ferroelectric, i.e. nonlinear polar material, in the form of ABO3 with A=Bi, B=Fe; [0052], [0039]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mathuriya et al. as applied to claims 1 and 5 above. Regarding claim 2, Mathuriya et al. teach the device structure of claim 1, wherein the first lateral thickness (the lateral thickness of bottom electrode of 1823b) is less than the second lateral thickness (the lateral thickness of 1811b of 1823b). Mathuriya et al. do not teach the first lateral thickness (the lateral thickness of bottom electrode of 1823b) is at least 2 nm less than the second lateral thickness (the lateral thickness of 1811b of 1823b) (emphasis added). Parameters such as the difference between teach the first lateral thickness (the lateral thickness of bottom electrode of 1823b) and the second lateral thickness (the lateral thickness of 1811b of 1823b), which determines the protected area of the bottom surface of 1811b using sidewall barrier seal ([0192]), in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired protection of the bottom of the stack of layers from hydrogen and/or oxygen diffusion ([0192]). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the difference between teach the first lateral thickness (the lateral thickness of bottom electrode of 1823b) and the second lateral thickness (the lateral thickness of 1811b of 1823b) within the range as claimed in order to achieve the desired protection of the bottom of the stack of layers from hydrogen and/or oxygen diffusion ([0192]). Regarding claim 6, Mathuriya et al. teach the device structure of claim 5, wherein the fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b) varies with height (see Fig. 18B). Mathuriya et al. do not teach wherein the fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b) is at least equal to a quarter of the vertical thickness (the vertical thickness of the bottom electrode of 1823b). Parameters such as the fourth lateral thickness (the lateral thickness of 1821e and a portion of 1821a in contact with 1811b of 1823b) and the vertical thickness (the vertical thickness of the bottom electrode of 1823b) in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired protection of the hydrogen and/or oxygen diffusion ([0192-0193] of Mathuriya et al.) and the potency of the ferroelectric material of the capacitor ([0194] of Mathuriya et al.). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the fourth lateral thickness and the vertical thickness within the range as claimed in order to achieve the desired protection of the hydrogen and/or oxygen diffusion ([0192-0193] of Mathuriya et al.) and the potency of the ferroelectric material of the capacitor ([0194] of Mathuriya et al.). Regarding claim 7, Mathuriya et al. teach the device structure of claim 6, wherein the first portion (1821e and a portion of 1821a in contact with 1811b of 1823b) and the second portion (the upper portion of 1821a above the top surface of 1811b of 1823b) are contiguous, and wherein the first portion (1821e and a portion of 1821a in contact with 1811b of 1823b) further comprises a cavity (a cavity between 1821e and a portion of 1821a in contact with 1811b of 1823b). Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mathuriya et al. as applied to claim 1 above, and further in view of Sato et al. (US 2023/0301113 A1). Regarding claim 3, Mathuriya et al. teach the device structure of claim 1, wherein the electrode structure (pedestal in contact with C1); wherein the second electrode (1811b of 1823b) comprises one of: a first non-Pb based metal oxide, such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer (W; [0194]); wherein the third electrode (top electrode of 1823b) comprises one of: a second non-Pb metal oxide (Fe2O3; [0197]), such as but not limited to, La(1-x)Sr(x)FeO3, La(1-x)Sr(x)CoO3, La(1-x)Ca(x)MnO3, La(1-x)Sr(x)MnO3, Ba(1-x)Sr(x)RuO3, La(1-x)Sr(x)MnO3, wherein 0 ≤ x ≤ 1, SrRuO3, Sr2RuO4, SrMoO3, SrCoO3, SrCrO3, SrFeO3, SrVO3, CaMoO3, SrNbO3, LaNiO3, YBa2Cu3O7, Bi2Sr2CaCuO8, CaRuO3, Ir, Ir2Oy, Ru, RuOy, Mo, MoOy, W, or WOy, wherein ‘y’ is an integer (W; [0198]), and wherein the first electrode (bottom electrode of 1823b) comprises one of: niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrogen doped variants of niobium, chromium, molybdenum, tantalum, tungsten, rhenium, titanium, nitrides of tantalum, tungsten, titanium, conductive doped AlN, or conductive doped SiN (tungsten; [0198]). Mathuriya et al. do not teach the electrode structure comprises: a conductive hydrogen barrier layer comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys; and a fill metal within the conductive hydrogen barrier layer, wherein the fill metal comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper. In the same field of endeavor of memory devices, Sato et al. teach the electrode structure (112; Fig. 1A, [0120]) comprises: a conductive hydrogen barrier layer (114; Fig. 1A, [0139]) comprising one of: TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent nitrogen, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, zinc oxide or METGLAS series of alloys (TiAlN with greater than 30 atomic percent AlN; [0140]); and a fill metal (fill material 115; Fig. 1A, [0139]) within the conductive hydrogen barrier layer (114), wherein the fill metal (fill material 115) comprises one of tantalum, titanium, ruthenium, tungsten, molybdenum or copper (fill material can be tantalum; [0240]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Mathuriya et al. and Sato et al., and to substitute the pedestal in contact with C1 in Fig. 16A of Mathuriya et al. with the electrode structure 112 in Fig. 1A of Sato et al., because the electrode structure 112 in Fig. 1A of Sato et al. can provide a bottom contact to the capacitor as the pedestal in contact with C1 in Fig. 16A of Mathuriya et al. and also has a conductive hydrogen barrier layer which can protect the memory device from diffusion of hydrogen into the device as taught by Sato et al. ([0145] of Sato et al.). Regarding claim 4, Mathuriya et al. teach the device structure of claim 3, wherein the electrode structure (pedestal in contact with C1) comprises a third lateral thickness (the lateral thickness of the pedestal in contact with C1; see Fig. 16A) that is less than the first lateral thickness (the lateral thickness of bottom electrode of 1823b; see Fig. 16A). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mathuriya et al. as applied to claim 9 above, and further in view of Lee et al. (US 2023/0034533 A1) and Hoshino (US 2006/0244102 A1). Regarding claim 10, Mathuriya et al. teach the device structure of claim 9, wherein the encapsulation structure (1821a-1821f of 1823b) comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are first and second integers, respectively (Al2O3; [0192]); and wherein the insulator (ILD) and the encapsulation structure (1821a-1821f of 1823b) comprise a different material ([0192]). Mathuriya et al. do not teach wherein the liner (etch stop layer in contact with the pedestal in contact with C1) comprises one of: silicon nitride, carbon doped silicon nitride, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, or TaSiOx, wherein ‘x’ and ‘y’ are third and fourth integers, respectively, wherein the insulator (ILD) comprises one of: silicon nitride, or carbon doped silicon nitride. In the same field of endeavor of semiconductor manufacturing, Lee et al. teach silicon nitride as the most common material for the etch stop layer ([0030] of Lee et al.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Mathuriya et al. and Lee et al., and to have the liner of Mathuriya et al. comprises silicon nitride, because Mathuriya et al. teach the liner to be a etch stop layer and Lee et al. teach silicon nitride as the most common material for the etch stop layer ([0030] of Lee et al.). In the same field of endeavor of semiconductor manufacturing, Hoshino teaches silicon nitride as one of the most common materials for ILD ([0035] of Hoshino). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Mathuriya et al. and Hoshino, and to have the insulator of Mathuriya et al. comprises silicon nitride, because Mathuriya et al. teach the insulator to be an ILD and Hoshino teach silicon nitride as one of the most common materials for the ILD ([0035] of Hoshino). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra V Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HSIN YI HSIEH/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Dec 16, 2023
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
51%
Grant Probability
57%
With Interview (+5.7%)
3y 11m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
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