CTNF 18/542,627 CTNF 101872 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 16, 2023 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. 23-19 AIA Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Drawings 06-22-07 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Fig. 6: Fig. 2: element 154 Fig. 8: element 100A . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections 07-29-01 AIA Claim is objected to because of the following informalities: Claim 13: . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-4, 6-10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Phatak et al. (US20160133691A1) . Regarding Claim 1: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) comprising: a substrate (Figs. 1 and 3 elements 101 and 301, paragraphs 53 and 73); a first electrode (first electrode layer; Figs. 1 and 3 elements 102 and 302, paragraphs 53 and 73) disposed above the substrate (Figs 1, 3 elements 101, 102, 301, and 302, paragraphs 53 and 73); a multilayer dielectric structure (bulk dielectric layer, first and second interface layers; Figs. 1 and 3 elements 104, 106, 108, 308 and 306) configured to cover the first electrode (Figs. 1 and 3 elements 102, 104, 106, 108, 302, 306 and 308, paragraphs 54-55 and 74); and a second electrode (second electrode layer; Figs. 1 and 3 elements 110 and 310) configured to cover the multilayer dielectric structure (Figs. 1 and 3 elements 104, 106, 108, 110, 306, 308 and 310, paragraphs 60 and 80), wherein the multilayer dielectric structure includes a plurality of dielectric films (bulk dielectric layer, first and second interface layers; Figs. 1 and 3 elements 104, 104A-B, 106, 108, 308, 306, and 304/8A-C), wherein a first dielectric film of the plurality of dielectric films first interface layer, bulk dielectric layer; Figs. 1 and 3 elements 104, 104A/B, 106, 306 and 308A-C) includes crystalline TiO2 or crystalline SrTiO3 (Figs. 2 and 4, paragraphs 5, 11, 49, 54, 55, 74 and 84), and wherein a second dielectric film of the plurality of dielectric films (second interface layer, bulk dielectric layer; Figs. 1 and 3 elements 106, 108, 306 and 308A-C) is in contact with the first dielectric film (Figs. 1 and 3 elements 104, 106, 108, 306 and 308) and includes a high-k dielectric film having a tetragonal crystal structure (paragraphs 5, 47 and 50). Regarding Claim 2: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the high-k dielectric film includes hafnium oxide or zirconium oxide (Figs. 2 and 4, paragraphs 55, 56, 64, 74, 75 and 86). Regarding Claim 3: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the high-k dielectric film (Fig. 3 element 308) includes a first high-k dielectric film (Fig. 3 element 308-A) and a second high-k dielectric film (Fig. 3 element 308-B) formed of different materials (Fig. 4, paragraphs 86-88), and wherein the first high-k dielectric film is in contact with the first dielectric film (Fig. 3 elements 306 and 308-A). Regarding Claim 4: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the crystalline TiO2 has a crystal structure of rutile, anatase, or brucite (paragraphs 47, 49, 58 and 77). Regarding Claim 6: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the first dielectric film has a dielectric constant of 40 or more (dielectric constant, k value; paragraphs 6, 9 and 54). Regarding Claim 7: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the multilayer dielectric structure has a thickness of 100 Å or less (Thk, thickness; Figs. 2 and 4). Regarding Claim 8: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 7, wherein the first dielectric film has a thickness of 10 Å to 30 Å (Thk, thickness; Figs. 2 and 4, paragraphs 54, 64 and 67). Regarding Claim 9: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 7, wherein the high-k dielectric film has a thickness of 5 Å to 20 Å (Thk, thickness; Figs. 2 and 4, paragraphs 56 and 65). Regarding Claim 10: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein the first dielectric film includes crystalline TiO2, and the high-k dielectric film includes tetragonal ZrO2 (Figs. 2 and 4, paragraphs 54, 71, 72 and 88) . 07-15 AIA Claim (s) 14-16, 18-19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lee et al. (US20220399435A1) . Regarding Claim 14: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) comprising: a substrate (Fig. 1 element 101, paragraph 20); a plurality of first electrodes (plurality of lower electrodes; Fig. 1 element 105, paragraph 20) disposed on the substrate (Fig. 1 elements 105 and 101, paragraph 20); a multilayer dielectric structure (a dielectric layer; Fig. 1 element 109) configured to cover the plurality of first electrodes (Fig. 1 elements 105 and 109, paragraph 20); and a second electrode (an upper electrode; Fig. 1 element 110) configured to cover the multilayer dielectric structure (Fig. 1 elements 110 and 109, paragraph 20), wherein the multilayer dielectric structure includes a plurality of dielectric films (paragraphs 24, 66 and 104), wherein the plurality of dielectric films include a first dielectric film and a second dielectric film formed of different materials (paragraphs 24 and 66), and a crystalline reinforced dielectric film having at least one surface in contact with the first dielectric film (paragraphs 24 and 66), and wherein the first dielectric film includes hafnium oxide (HfO2) or zirconium oxide (ZrO2), and the crystalline reinforced dielectric film includes crystalline TiO2 or crystalline SrTiO3 (paragraphs 24 and 66). Regarding Claim 15: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) according to claim 14, wherein the first dielectric film includes a tetragonal zirconium oxide (paragraphs 24, 29 and 31), and the crystalline reinforced dielectric film includes crystalline TiO2 (paragraphs 24, 66 and 104). Regarding Claim 16: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) according to claim 15, wherein the second dielectric film includes a material selected from the group consisting of hafnium oxide, aluminum oxide, yttrium oxide, scandium oxide, and lanthanum oxide (paragraphs 24 and 28). Regarding Claim 18: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) according to claim 14, further comprising: a first interface layer (booster layer; Figs. 1 and 8 element 108) disposed between the plurality of first electrodes and the multilayer dielectric structure (Figs. 1 and 8 elements 105, 108, and 109, paragraph 20); and a second interface layer (interface layer; Fig. 8 element 111) disposed between the second electrode and the multilayer dielectric structure (Fig. 8 elements 110, 109, and 111, paragraph 100). Regarding Claim 19: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) according to claim 18, wherein each of the first interface layer and the second interface layer includes an oxide or a nitride including at least one element selected from the group consisting of Ta, Sb, Mo, Co, Nb, Cu, Ni, V, and W (paragraphs 28 and 100) . 07-15 AIA Claim 20 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kang et al. (US20200395438A1) . Regarding Claim 20: Kang discloses a semiconductor device (integrated circuit device; Figs. 2, 4, 6, 8 and 10 elements 100A-D, paragraph 28) comprising: a device isolation layer (device isolation film; Fig. 2 element 112, paragraph 29) configured to define active regions (active regions AC; Fig. 2 element AC, paragraph 29) on a substrate (Fig. 2 element 110, paragraph 29); gate electrodes (gate structure; Fig. 2 elements 120 and 120T) intersecting the active regions (Fig. 2 elements 120, 120T and AC, paragraph 32) and extending into the device isolation layer (Fig. 2 elements 120, 120T and 112, paragraph 32); first impurity regions (first source/drain region; Fig. 2 element 114A, paragraph 33) and second impurity regions (second source/drain region; Fig. 2 element 114B, paragraph 33) disposed within the active regions on opposite sides of the gate electrodes (Fig. 2 elements AC, 114A-B, 120T and 120, paragraph 33); bit lines (bit line structure; Fig. 2 element 130, paragraph 38) disposed at a higher level than the gate electrodes and connected to the first impurity regions (Fig. 2 elements 114A, 120 and 130, paragraph 38); conductive patterns disposed on side surfaces of the bit lines and connected to the second impurity regions (capacitor contact and landing pad Fig. 2 elements 114B, 150 and 152, paragraphs 41 and 42); a plurality of first electrodes (bottom electrode; Fig. 2 element 170) extending vertically on the conductive patterns and connected to each of the conductive patterns (Fig. 2 elements 170, 150 and 152, paragraphs 44 and 47-48); at least one support layer (supporter; Figs. 2-3 elements 192 and 194) spaced apart from an upper surface of the substrate in a vertical direction, extending in a direction parallel to the upper surface of the substrate (Fig. 2 elements 110, 192 and 194, paragraph 51), and contacting a side surface of each of adjacent first electrodes among the plurality of first electrodes (Fig. 3 elements 170, 192S and 192, paragraph 51); a multilayer dielectric structure (dielectric layer; Figs. 2 and 3 element 180) configured to cover the plurality of first electrodes and the support layer (Figs. 2-3 elements 180, 170 and 192, paragraphs 44 and 54); and a second electrode (top electrode; Figs. 2-3 element 185) configured to cover the multilayer dielectric structure (Fig. 3 element 180 and 185, paragraphs 44 and 56), wherein the multilayer dielectric structure includes a first dielectric film and a second dielectric film formed of different materials (first and second dielectric layers; Fig. 2 element 180, paragraph 55), and a crystalline reinforced dielectric film having at least one surface in contact with the first dielectric film (interfacial layer; paragraph 58), and wherein the first dielectric film includes hafnium oxide (HfO2) or zirconium oxide (ZrO2) (paragraphs 55, 59 and 67), and the crystalline reinforced dielectric film includes crystalline TiO2 or crystalline SrTiO3 (paragraphs 55 and 58) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (US20160133691A1) in view of Morishita et al. (US20230055097A1) . Regarding Claim 5: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein Phatak discloses the use of a film comprising of a crystalline SrTiO3 material, but does not explicitly disclose the material having the property of a perovskite crystal structure. Morishita – an analogous art – also teaches a crystalline material, in a thin film device, consisting of a perovskite-type oxide such as SrTiO3 (paragraphs 3 and 154). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a general understanding about properties that are known in Phatak, such that a perovskite crystal structure is an inherent property of crystalline SrTiO3. Using this specific crystal material aids in the improvements to the performance of electronic devices (Morishita, paragraph 3) . 07-21-aia AIA Claim (s) 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (US20160133691A1) in view of Trinh et al. (US20230387190A1) . Regarding Claim 11: Phatak discloses a semiconductor device (Figs. 1 and 3 elements 100 and 300) according to claim 1, wherein there is a multilayer dielectric structure (bulk dielectric layer, first and second interface layers; Figs. 1 and 3 elements 104, 106, 108, 308 and 306) within the semiconductor device, but does not explicitly disclose an insertion layer disposed within and among the plurality of dielectric films nor the layer to include an oxide or a nitride containing trivalent or pentavalent metal. Trinh discloses an analogous multilayer dielectric structure (intermediate structure; Figs. 2 and 3 elements 2a-b, paragraphs 24-26 and 30) within a capacitor structure and electronic device, that further includes an insertion layer (intermediate dielectric layer; Figs. 1, 2 and 3 elements 13 and 23) disposed between adjacent dielectric films among the plurality of dielectric film (Figs. 1, 2 and 3 elements 21, 22 and 23, paragraphs 24 and 26); wherein the insertion layer includes an oxide or a nitride containing trivalent or pentavalent metal (paragraphs 18, 21 and 55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device described in Phatak further in view of Trinh to include an insertion layer – comprising an of an oxide or a nitride containing trivalent or pentavalent metal – between adjacent dielectric films because both are directed to analogous multilayer dielectric structures within a semiconductor device. Doing so aids to achieve an increase in capacitance density in capacitors while mitigating leakage issues that arise (Trinh, paragraph 0001). Regarding Claim 12: The combination of Phatak and Trinh discloses a semiconductor device according to claim 11, but Phatak does not explicitly disclose an insertion layer which includes an oxide or a nitride containing a metal selected from the group consisting of Al, Y, La, B, In, V, Ta, and Nb. Trinh discloses an insertion layer (intermediate dielectric layer; Figs. 1, 2 and 3 elements 13 and 23) that includes an oxide or a nitride containing a metal selected from the group consisting of Al, Y, La, B, In, V, Ta, and Nb (paragraphs 18, 21 and 55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device described in Phatak further in view of Trinh such that the insertion layer includes an oxide or a nitride containing a metal selected from the group consisting of Al, Y, La, B, In, V, Ta, and Nb such as TaxAl1-xO. Doing so can result in lower leakage and/or higher capacitance (Trinh, paragraph 18) Regarding Claim 13: The combination of Phatak and Trinh discloses a semiconductor device according to claim 11, but Phatak does not explicitly disclose an insertion layer that has a thickness of 0.05 Å to 5 Å. Trinh discloses an insertion layer (intermediate dielectric layer; Figs. 1, 2 and 3 elements 13 and 23) wherein the thickness is between 0.05 Å to 5 Å (paragraph 20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device described in Phatak further in view of Trinh such that the insertion layer has a thickness of 0.05 Å to 5 Å, such as greater than 2 Å but less than 5 Å. Doing so allows for greater improvements in the miniaturization of integrated circuits while also providing more functionality at higher speeds (Trinh, paragraph 1) . 07-21-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20220399435A1) in view of Trinh et al. (US20230387190A1) . Regarding Claim 17: Lee discloses a semiconductor device (Fig. 1 element 100, paragraph 20) according to claim 14, and a multilayer dielectric structure (a dielectric layer; Fig. 1 element 109), but does not explicitly disclose a first and second insertion layer disposed within the structure nor that the insertion layers include an oxide or a nitride containing a metal of different valence from each other. Trinh discloses an analogous multilayer dielectric structure (intermediate structures; Figs. 3 elements 1a-c, paragraph 31) within a capacitor structure and electronic device, that includes a first insertion layer (an intermediate layer; Fig. 3 elements 1a and 13) disposed between adjacent dielectric films among the plurality of dielectric films (Fig. 3 elements 1a, 11, 12 and 13, paragraph 33). A second insertion layer disposed between other adjacent dielectric films among the plurality of dielectric films (Fig. 3 elements 1b and 13, paragraph 35), and wherein each of the first and second insertion layers (intermediate layers; Fig. 3 elements 1a, 1b and 13) includes an oxide or a nitride containing a metal of different valence from each other (paragraphs 18, 21 and 55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device described in Lee further in view of Trinh to include a first and second insertion layer disposed between adjacent dielectric films among the plurality of dielectric films – wherein each of the layers includes an oxide or a nitride containing a metal of different valence from each other – because both are directed to analogous multilayer dielectric structures within a semiconductor device. Doing so aids to achieve an increase in capacitance density in capacitors while mitigating leakage issues that arise (Trinh, paragraphs 1 and 18). Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al. (US 20230215910 A1), Kang et al. (US 20210202693 A1), Moser et al. (US 20060006382 A1), Spanier et al. (US 20220013288 A1), and Kang et al. (US 20210359082 A1) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chloë E Benton/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/542,627 Page 2 Art Unit: 2899 Application/Control Number: 18/542,627 Page 3 Art Unit: 2899 Application/Control Number: 18/542,627 Page 5 Art Unit: 2899 Application/Control Number: 18/542,627 Page 6 Art Unit: 2899 Application/Control Number: 18/542,627 Page 7 Art Unit: 2899 Application/Control Number: 18/542,627 Page 8 Art Unit: 2899 Application/Control Number: 18/542,627 Page 9 Art Unit: 2899 Application/Control Number: 18/542,627 Page 10 Art Unit: 2899 Application/Control Number: 18/542,627 Page 11 Art Unit: 2899 Application/Control Number: 18/542,627 Page 12 Art Unit: 2899 Application/Control Number: 18/542,627 Page 13 Art Unit: 2899 Application/Control Number: 18/542,627 Page 14 Art Unit: 2899
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