DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see p. 7, 2nd paragraph, filed February 17, 2026, with respect to the objections have been fully considered and are persuasive. The objections to Claims 3, 10, and 17 have been withdrawn.
Applicant's arguments filed February 17, 2026, with respect to Claims 1-20 have been fully considered but they are not persuasive. Applicant argues that Lee (US 20240046842A1) does not disclose the specific timing relationship in which a variable refresh rate circuit that provides instructions in a first video frame to display a first dithered frame segment of the first video frame during reception of a second video frame, followed by switching to display of a second dithered frame segment of a second video frame based on instructions in the second video frame. This specific temporal coordination of display and reception operations is not disclosed by Lee. Rather, Lee discusses activation/deactivation of dithering based on frame frequency changes (p. 7, last paragraph-p. 8, 1st paragraph).
In reply, the Examiner points out that Lee describes “dithering circuit 320 outputs dithered image data DDAT by performing dithering on the first image data DAT…dithering circuit 320 may perform dithering on at least a portion of the first image data DAT based on at least one of dither algorithms” [0081]. Fig. 12B shows receiving another image frame in S231. Thus, Lee teaches providing a first dithered segment of the first video frame comprising instructions to display the first dithered segment [0081] during reception of a second video frame (S231). Lee describes “selectively activates the dithering on the first image data DAT based on the frame frequency. The display device 100 may activate the dithering when the frame frequency is rapidly decreased…operation S230…may be performed based on whether a difference between frame frequencies of the first and second image frames is greater than a threshold value. When the frame frequency of the second image frame is lower than the frame frequency of the first image frame and the difference between the frame frequencies of the first and second image frames is greater than the threshold value, the dithering may be activated” [0110]. Thus, when the frame frequency of the second image frame is lower than the frame frequency of the first image frame and the difference between the frame frequencies of the first and second image frames is greater than the threshold value, this means that it is taking a long time to receive the second video frame, and thus it provides a first dithered segment of the first video frame comprising instructions to display the first dithered segment during reception of a second video frame. Lee describes “after the dithering is activated…in operation S231…after reception of the second image frame” [0116]. Thus, the second video frame is received and display of the first dithered segment is completed. Lee describes “it is determined whether the frame frequency of the third image frame is higher than the reference frequency…when the frame frequency of the third image frame is not higher than the reference frequency, operation S234 is performed…activation of the dithering is maintained in operation S234” [0116]. Thus, when the frame frequency of the third image frame is not higher than the reference frequency, this means that it is taking a long time to receive the third image frame, and thus it provides a second dithered segment of the second video frame comprising instructions to display the second dithered segment. Thus, responsive to reception of the second video frame and completion of display of the first dithered segment, and it is taking a long time to receive the third frame, providing a second dithered segment of the second video frame comprising instructions to display the second dithered segment. Thus, Lee teaches the limitations as they are recited in Claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 20240046842A1).
As per Claim 1, Lee teaches a display controller including: a variable refresh rate circuit (controller which controls a driving of the data driver by processing image data input thereto at a variable refresh rate, Abstract) configured to: receive a first video frame (S210) (in operation S210, the sequentially input first and second image frames are received as the stream of first image data, [0110]). Lee describes “dithering circuit 320 outputs dithered image data DDAT by performing dithering on the first image data DAT…dithering circuit 320 may perform dithering on at least a portion of the first image data DAT based on at least one of dither algorithms” [0081]. Fig. 12B shows receiving another image frame in S231. Thus, Lee teaches providing a first dithered segment of the first video frame comprising instructions to display the first dithered segment [0081] during reception of a second video frame (S231). Lee describes “selectively activates the dithering on the first image data DAT based on the frame frequency. The display device 100 may activate the dithering when the frame frequency is rapidly decreased…operation S230…may be performed based on whether a difference between frame frequencies of the first and second image frames is greater than a threshold value. When the frame frequency of the second image frame is lower than the frame frequency of the first image frame and the difference between the frame frequencies of the first and second image frames is greater than the threshold value, the dithering may be activated” [0110]. Thus, when the frame frequency of the second image frame is lower than the frame frequency of the first image frame and the difference between the frame frequencies of the first and second image frames is greater than the threshold value, this means that it is taking a long time to receive the second video frame, and thus it provides a first dithered segment of the first video frame comprising instructions to display the first dithered segment during reception of a second video frame. Lee describes “after the dithering is activated…in operation S231…after reception of the second image frame” [0116]. Thus, the second video frame is received and display of the first dithered segment is completed. Lee describes “it is determined whether the frame frequency of the third image frame is higher than the reference frequency…when the frame frequency of the third image frame is not higher than the reference frequency, operation S234 is performed…activation of the dithering is maintained in operation S234” [0116]. Thus, when the frame frequency of the third image frame is not higher than the reference frequency, this means that it is taking a long time to receive the third image frame, and thus it provides a second dithered segment of the second video frame comprising instructions to display the second dithered segment. Thus, responsive to reception of the second video frame and completion of display of the first dithered segment, and it is taking a long time to receive the third frame, providing a second dithered segment of the second video frame comprising instructions to display the second dithered segment.
As per Claim 7, Lee teaches the display device activates the dithering when the frame frequency is rapidly decreased. When the frame frequency of the second image frame is lower than the frame frequency of the first image and the difference between the frame frequencies of the first and second image frames is greater than the threshold value, the dithering is activated [0110]. Thus, when the source frame rate of the first video frame and the second video frame is rapidly decreased, then the dithering is activated in order to output a dithered segment faster without having to wait for the second video frame, and thus the display frame rate is faster than the source frame rate of the first video frame and the second video frame. Thus, wherein the variable refresh rate circuit is configured to provide a display frame rate that is different from a source frame rate of the first video frame and the second video frame [0110].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 3, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) in view of Au (US 20050001809A1).
As per Claim 2, Lee is relied upon for the teachings as discussed above relative to Claim 1.
However, Lee does not expressly teach wherein the display controller includes a buffer configured to store the second video frame, and the variable refresh rate circuit is configured to provide the second dithered segment responsive to completion of storage of the second video frame in the buffer. However, Au teaches FIFO memory 20 receives data and the data is read out in the order in which it is stored. The FIFO memory 20 is used to store a stream of pixels a portion at a time. The FIFO memory 20 keeps a stream of pixels available to be displayed on the LCD [0023]. The data converter 22 performs operations such as dithering [0024]. A display data generator 26 is connected to the data converter 22 for receiving the converted data and generating temporary display data therefrom. The temporary display data is then stored in a holding register 28. That is, in order to provide display data to the LCD, even under the condition where the FIFO memory unit 20 needs new data but the system bus is unable to provide new data, for instance, due to a bus over load condition, the present invention includes a means for generating and holding a line of temporary display data that can be provided to the LCD when the FIFO memory unit 20 is unable to provide display data. The display data generator 26 generates a next line of display data that can be provided to the LCD when the FIFO memory 20 is unable to provide the next line of data, in order to reduce image flicker [0026]. Thus, when the second video frame is stored in the FIFO memory unit 20, but the FIFO memory unit 20 is unable to provide display data (bus over load condition), then it provides the temporary display data from the display data generator 26, which received the converted data from the data converter 22, which performed dithering, and thus the temporary display data is the dithered data, and thus the dithered data is output faster than waiting for the second video frame to be output from the FIFO memory unit 20, and thus the refresh rate is increased [0023, 0024, 0026]. Thus, Au teaches wherein the display controller includes a buffer configured to store the second video frame, and the variable refresh rate circuit is configured to provide the second dithered segment responsive to completion of storage of the second video frame in the buffer [0023, 0024, 0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee so that the display controller includes a buffer configured to store the second video frame, and the variable refresh rate circuit is configured to provide the second dithered segment responsive to completion of storage of the second video frame in the buffer because Au suggests that it is well-known in the art to have a FIFO to reduce the probability of bus overload [0004].
As per Claim 3, Lee does not expressly teach wherein the display controller includes a buffer subdivided into a plurality of sub-buffers configured to store the second video frame, and the variable refresh rate circuit is configured to provide the second dithered segment responsive to completion of storage of a portion of the second video frame in one of the sub-buffers. However, Au teaches the FIFO memory unit 20 [0023]. It is well-known in the art that a FIFO memory unit is an array of continuous memory to store data. Data is written to the head of the buffer and read from the tail. Since the FIFO memory unit is a buffer that is an array of continuous memory, it would have been obvious to one of ordinary skill in the art that this could be considered to be a buffer subdivided into a plurality of sub-buffers. Thus, Au teaches wherein the display controller includes a buffer subdivided into a plurality of sub-buffers configured to store the second video frame, and the variable refresh rate circuit is configured to provide the second dithered segment responsive to completion of storage of a portion of the second video frame in one of the sub-buffers [0023, 0024, 0026]. This would be obvious for the reasons given in the rejection for Claim 2.
As per Claim 5, Lee does not expressly teach wherein: the display controller is configured to provide the first video frame as first, second, and third color segments; and the variable refresh rate circuit is configured to provide the color segments until reception of the second video frame. However, Au teaches FIFO memory 20 receives data and the data is read out in the order in which it is stored. The FIFO memory 20 is used to store a stream of pixels a portion at a time. The FIFO memory 20 keeps a stream of pixels available to be displayed on the LCD [0023]. Thus, the FIFO memory 20 outputs a portion of pixels at a time. Thus, Au teaches wherein: the display controller is configured to provide the first video frame as first, second, and third color segments; and the variable refresh rate circuit is configured to provide the color segments until the reception of the second video frame [0023, 0024, 0026]. This would be obvious for the reasons given in the rejection for Claim 2.
15. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) in view of Yoon (US 20130222549A1).
Lee is relied upon for the teachings as discussed above relative to Claim 1.
However, Lee does not expressly teach wherein the variable refresh rate circuit is configured to adjust a display frame rate based on a time between reception of the first video frame and reception of the second video frame. However, Yoon teaches wherein the variable refresh rate circuit is configured to adjust a display frame rate based on a time between reception of the first video frame and reception of the second video frame (first timing information indicating frame start information of first image data and second timing information indicating a frame start information of second image data, [0014], change the frame rate if the difference between the first timing information and the second timing information is above a threshold, [0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee so that the variable refresh rate circuit is configured to adjust a display frame rate based on a time between reception of the first video frame and reception of the second video frame because Yoon suggests that this increases the quality of images displayed [0002].
16. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) and Au (US 20050001809A1) in view of Albrecht (US 20150379970A1).
Lee and Au are relied upon for the teachings as discussed above relative to Claim 5.
However, Lee and Au do not expressly teach wherein: the color segments include multiple dithered segments; and the variable refresh rate circuit is configured to provide the second dithered segment of the second video frame responsive to completion of display of one of the color segments or completion of display of the first video frame. However, Albrecht teaches wherein: the color segments include multiple dithered segments (to introduce color noise, dithering patterns may be applied to the source image, applying the dithering patterns may spatially distribute the colors of the source image, [0055]). When the determined refresh rate is less than a threshold refresh rate of the electronic device, the electronic display spatially dithers the image data and displays the image based on the spatially dithered image data (Abstract). Thus, when the determined refresh rate is less than a threshold refresh rate of the electronic device, this means that the first video frame has been displayed, but the second video frame is not ready yet, and thus it provides a dithered segment, and thus the dithered segment is output faster instead of having to wait for the second video frame, and thus this increases the refresh rate to the threshold refresh rate. Thus, the variable refresh rate circuit is configured to provide the second dithered segment of the second video frame responsive to completion of display of one of the color segments or completion of display of the first video frame (Abstract) [0055].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee and Au so that the color segments include multiple dithered segments; and the variable refresh rate circuit is configured to provide the second dithered segment of the second video frame responsive to completion of display of one of the color segments or completion of display of the first video frame because Albrecht suggests that this enables the display of the image at a lower pixel depth while significantly preserving the perceived image quality [0055].
17. Claim(s) 8-10, 12-14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) in view of Favalora (US 20020135673A1), Au (US 20050001809A1), and Albrecht (US 20150379970A1).
18. As per Claim 8, Lee teaches a method comprising: receiving, by a display controller, a first video frame (S210) [0110]; providing, by the display controller, the first video frame as dithered data to a display [0110, 0081]; receiving, by the display controller, a second video frame (S231) while the first video frame is being displayed by the display; and providing by the display controller, a dithered segment of the second video frame to the display responsive to receipt of the second video frame and completion of display of a dithered segment of the first video frame [0110, 0081, 0115, 0116], as discussed in the rejection for Claim 1.
However, Lee does not teach that the display is a spatial light modulator (SLM). However, Favalora teaches a spatial light modulator (SLM) that is dithered during a frame [0045, 0096]. Thus, this teaching of the SLM from Favalora can be implemented into the display of Lee so that the display is a SLM.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee so that the display is a SLM as suggested by Favalora. It is well-known in the art that SLMs can produce natural-looking 3D images that blend with the environment, providing a more realistic experience without special glasses.
However, Lee and Favalora do not expressly teach providing the first video frame as a first, second, and third color segments, in which the color segments include multiple dithered segments. However, Au and Albrecht teach these limitations, as discussed in the rejections for Claims 5-6.
19. As per Claims 9, 10, and 12-14, these claims are similar in scope to Claims 2, 3, and 5-7 respectively, and therefore are rejected under the same rationale. As per Claim 20, Claim 20 is similar in scope to Claim 6, and therefore is rejected under the same rationale.
20. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1), Favalora (US 20020135673A1), Au (US 20050001809A1), and Albrecht (US 20150379970A1) in view of Yoon (US 20130222549A1).
Claim 11 is similar in scope to Claim 4, and thus is rejected under the same rationale.
21. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) in view of Favalora (US 20020135673A1).
Lee teaches a system comprising: a display (110, Fig. 1) (display panel 110, [0058]); and a display controller (200, Fig. 3) (timing controller 200, [0074]) including: a video input (timing controller 200 may include an image signal processor 210, [0074], image signal processor 210 may process the first image data DAT, [0075]), a display control output coupled to an input of the display (timing controller may transmit a first control signal CONT1 to the data driver 150, transmit a second control signal CONT2 to the gate driver 140, [0062], Fig. 1 shows that the timing controller outputs CONT1 and CONT2 to the data driver 150 and the gate driver 140, which output to the display panel 110), and a variable refresh rate circuit (Abstract) configured to: receive, via the video input, a first video frame (S210) [0110]; instruct, via the display control output, the display to display a first dithered segment of the first video frame [0110, 0081] during reception of a second video frame (S231); and responsive to reception of the second video frame and completion of display of the first dithered segment [0110, 0081, 0115, 0116], instruct, via the display control output, the display to display a second dithered segment of the second video frame [0116], as discussed in the rejection for Claim 1.
However, Lee does not teach that the display is a spatial light modulator (SLM). However, Favalora teaches this, as discussed in the rejection for Claim 8.
22. Claim(s) 16, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) and Favalora (US 20020135673A1) in view of Au (US 20050001809A1).
As per Claim 16, Claim 16 is similar in scope to Claim 9, and therefore is rejected under the same rationale. As per Claims 17 and 19, these claims are similar in scope to Claims 3 and 5 respectively, and therefore are rejected under the same rationale.
23. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20240046842A1) and Favalora (US 20020135673A1) in view of Yoon (US 20130222549A1).
Claim 18 is similar in scope to Claim 4, and thus is rejected under the same rationale.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONI HSU whose telephone number is (571)272-7785. The examiner can normally be reached M-F 10am-6:30pm.
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JH
/JONI HSU/Primary Examiner, Art Unit 2611