DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/17/2023 and 9/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 11-13 and 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 19 of U.S. Patent Appl. Pub. No. 2024/0213292 A1. Although the claims at issue are not identical, they are not patentably distinct from each other.
[Re claim 1] Reference (US 2024/0213292) discloses the micro light-emitting diode (LED) structure, comprising: an integrated circuit (IC) back plane; a stack of mesa structures comprising: a first mesa structure on the IC back plane, and a second mesa structure on the first mesa structure; and a dielectric layer between the first and second mesa structures, wherein the first mesa structure comprises: a first light emitting layer (first epitaxial layer, quantum well layer and second epitaxial layer), a first connecting layer formed on and electrically connected to the first light emitting layer, and a first conductive bonding layer formed under the first light emitting layer and electrically connecting the first light emitting layer to the IC back plane; wherein the second mesa structure comprises: a second light emitting layer (first epitaxial layer, quantum well layer and second epitaxial layer), a second connecting layer formed on and electrically connected to the second light emitting layer, a second conductive bonding layer formed under the second light emitting layer, and a third connecting layer formed under the second conductive bonding layer and electrically connected to the second light emitting layer via the second conductive bonding layer (see claim 1-3).
[Re claim 2] Reference (US 2024/0213292) discloses the micro LED structure, wherein, in plan view, an outline of the second mesa structure is disposed within an outline of the first mesa structure (see claim 2).
[Re claim 3] Reference (US 2024/0213292) discloses the micro LED structure wherein sidewalls of the first and second conductive bonding layers are respectively aligned with sidewalls of the first and second light emitting layers (see claim 4).
[Re claim 11] Reference (US 2024/0213292) discloses the micro LED structure wherein each of the first and second conductive bonding layers comprises a metal, a composite metal, or a transparent conductive material (see claim 5).
[Re claim 12] Reference (US 2024/0213292) discloses the micro LED structure wherein the transparent conductive material is SiO2 or ITO (see claim 6).
[Re claim 13] Reference (US 2024/0213292) discloses the micro LED structure wherein each of the first, second, and third connecting layers comprises a transparent conductive material (see claim 19).
[Re claim 17] Reference (US 2024/0213292) discloses the micro LED structure wherein each of the first and second light emitting layers comprises a P-type semiconductor layer (first conductive type) and an N-type semiconductor layer (second conductive type), the P- type semiconductor layer and N-type semiconductor layer forming a P-N junction (see claim 1).
[Re claim 18] Reference (US 2024/0213292) discloses the micro LED structure wherein each of the first and second light emitting layers further comprises a quantum well layer formed between the P-type semiconductor layer and the N-type semiconductor layer (see claim 1).
[Re claim 19] Reference (US 2024/0213292) discloses the micro LED structure wherein the stack of mesa structures further comprises a third mesa structure formed on the second mesa structure, the third mesa structure comprising: a third light emitting layer, a forth connecting layer formed on and electrically connected to the third light emitting layer, a third conductive bonding layer formed under the third light emitting layer, and a fifth connecting layer formed under the third conductive bonding layer and electrically connected to the third light emitting layer through the third conductive bonding layer (see claim 1-3).
Allowable Subject Matter
Claims 4-10, 14-16 and 21-24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 allowed.
The following is an examiner's statement of reasons for allowance: Claim 20 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the full color micro LED panel, wherein the first mesa structure comprises: a first light emitting layer, a first connecting layer formed on and electrically connected to the first light emitting layer, and a first conductive bonding layer formed under the first light emitting layer and electrically connecting the first light emitting layer to the IC back plane; wherein the second mesa structure comprises: a second light emitting layer, a second connecting layer formed on and electrically connected to the second light emitting layer, a second conductive bonding layer formed under the second light emitting layer, and a third connecting layer formed under the second conductive bonding layer and electrically connected to the second light emitting layer via the second conductive bonding layer. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817