DETAILED ACTION
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “sacrificial material 11” in paragraphs 42-45 for Figs. 2A and 2B. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wernersson et al. (US 2021/0280700 A1; hereinafter “Wernersson”).
Regarding claim 1, Wernersson teaches a semiconductor structure comprising:
a semiconductor element (a vertical nanowire 102) of a semiconductor device (a vertical MOSFET), wherein a portion of the semiconductor element crosses a sidewall plane of a metal element (a vertical sidewall of a metal/gate layer of a wrap-around gate 150 from a gate stack layer 110) (Figs. 1A-1G and paragraphs 88-89 and 95-97); and
a dielectric material (a high-k dielectric layer of 150) on the portion of the semiconductor element (i) contacting the metal element and (ii) electrically isolating the semiconductor element from the metal element (the high-k dielectric layer of 150 is contacting the metal/gate layer of 150 and electrically isolating 102 from the metal/gate layer of 150) (Figs. 1A-1G and paragraph 95).
Regarding claim 3, Wernersson teaches wherein the dielectric material on the portion of the semiconductor element is a spacer (the high-k dielectric layer of 150 is a spacer between 102 and the metal/gate layer of 150) (Figs. 1A-1G and paragraph 95).
Regarding claim 11, Wernersson teaches wherein the metal element is at least one element selected from the group of consisting a contact, a via, and a line (the metal/gate layer of 150 is a conductive line) (paragraph 95), and wherein the semiconductor element is at least one element selected from the group consisting of a channel, a layer of a capacitor, a substrate, and a source/drain (the nanowire 102 of the vertical MOSFET would function as a channel at the middle region of 102 for the vertical MOSFET) (Fig. 1G and paragraph 88).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Wernersson.
Regarding claim 2, while Wernersson does not explicitly teach that the semiconductor element (the nanowire 102 of the vertical MOSFET) is a source/drain of a field-effect transistor, it would have been obvious to one of ordinary skill in the art to recognize that a top portion of the nanowire 102 in an electrical contact with a top contact 194 from Wernersson in Fig. 1G would function as the source/drain region of the nanowire 102 for the vertical MOSFET for providing the functional vertical MOSFET.
Regarding claim 4, while Wernersson does not explicitly teach a thickness range in a numerical value for the dielectric material (the high-k dielectric layer of 150 as a gate dielectric layer), it would have been obvious to one of ordinary skill in the art to adjust the thickness of the dielectric material in a desired range, including the claimed thickness of 3-5 nm, as a routine experimentation for obtaining the optimal thickness for the dielectric material.
Allowable Subject Matter
Claims 5-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-16 are allowable over the cited prior arts.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor structure in claim 12, particularly in combination with the limitation that a second top source/drain of the second L-shaped stacked GAAFET has a narrower width than a width of a second bottom source/drain of the second L- shaped stacked GAAFET; the first top source/drain of the first top GAAFET has a first dielectric layer on a first sidewall; wherein the first dielectric layer contacts a first via; a second sidewall of the first top source/drain electronically contacts a second via; the first bottom source/drain of the first bottom GAAFET has a second dielectric layer on a third sidewall the second dielectric contacting the second via; and the second dielectric layer contacts a backside power via connecting to a backside metal layer. The cited prior arts are Chen et al. (US 2024/0313065 A1) and Xie et al. (US 2023/0065715 A1) and Wernersson et al. (US 2021/0280700 A1).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot in view of new ground of rejection as set forth above in this Office Action by Wernersson et al. (US 2021/0280700 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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