DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, with corresponding claims 1-16, in the reply filed on 03/23/2026 is acknowledged. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SELF-ALIGNED DIELECTRIC ISOLATION ON SOURCE/DRAIN OF GATE-ALL-AROUND NANOSHEET MOSFET
Claim Objections
Claims 6, 9-11, and 16 are objected to because of the following informalities:
Regarding claim 6, “each of the two vertically stacked field-effect transistors are…each of the vertically stacked gate-all-around field-effect transistor have” in lines 1-3 should be changed to “each of the two vertically stacked field-effect transistors is…each of the vertically stacked gate-all-around field-effect transistors has”.
Regarding claim 9, “where each of the plurality of source/drain contacts connect…frontside interconnect wiring” in lines 3-5 should be changed to “wherein each of the plurality of source/drain contacts connects…a frontside interconnect wiring”.
Regarding claim 10, “each of a plurality of gate contacts each connect” in line 2 should be changed to “each of a plurality of gate contacts connects”.
Regarding claim 11, “the group of consisting” in line 2 should be changed to “the group consisting of”.
Regarding claim 16, “frontside interconnect wiring” in line 3 should be changed to “a frontside interconnect wiring”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 and 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the limitation “a first source/drain of a bottom gate-all-around field-effect transistor connecting by a backside contact to a backside metal layer; and a second source/drain of a bottom gate-all-around field-effect transistor connecting by the backside contact to the backside metal layer” would render the claim indefinite since it is unclear what “connecting by” is directed to.
Regarding claim 9, the limitation “a plurality of source/drain contacts to a plurality of source/drains of a top gate-all-around field-effect transistor, where each of the plurality of source/drain contacts connect the plurality of source/drains” would render the claim indefinite since 1) it appears that there is a grammatical error for “a plurality of source/drain contacts to a plurality of source/drains of a top gate-all-around field-effect transistor” with missing a verb after “a plurality of source/drain contacts” and 2) “a plurality of source/drains” is unclear why there is singular “source” and plural “drains”. Should, for example, “a plurality of source/drains” be rather “a plurality of source/drain regions”?
Claim 10 similarly recites “a plurality of source/drains” and therefore renders the claim indefinite with the similar reason for rejecting claim 9 as discussed above.
Regarding claim 12, First, the limitation “wherein the top source/drain has a narrower width than the width of a bottom source/drain” would render the claim indefinite since it is unclear what “the top source/drain” is referring to between “a top source/drain of the first top gate-all-around field-effect transistor” previously recited and a top source/drain of the second top stacked gate-all-around field-effect transistor and what “a bottom source/drain” is referring to between “a bottom source/drain of the first bottom gate-all-around field-effect transistor” previously recited and a bottom source/drain for the second L-shaped stacked gate-all-around field-effect transistor. Second, “the top source/drain” is also recited in line 16 without clarifying which transistor’s top source/drain “the top source/drain” is directed to. Third, the same terms “a dielectric material” are twice recited in lines 11 and 13. Fourth, “a dielectric material” on a left sidewall of the top source/drain of the first top gate-all-around field-effect transistor and “the dielectric material” on the right sidewall of the bottom source/drain of the first bottom gate-all-around field-effect transistor appear to be two different dielectric material portions while using the same term. Therefore, it is unclear to one of ordinary skill in the art to determine the metes and bounds of the claimed limitation. Claims 13-16, which depend from claim 12, are also rejected by virtue of their dependencies.
Regarding claim 14, “the first top source/drain and the first bottom source/drain” would render the claim indefinite since “the first top source/drain” and “the first bottom source/drain” are not clearly defined which transistor’s “the first top source/drain” and “the first bottom source/drain” is.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 2024/0313065 A1; hereinafter “Chen”).
Regarding claim 1, Chen teaches a semiconductor structure comprising: a semiconductor element (source and drain structures 180) of a semiconductor device (a gate all around transistor) (paragraphs 20 and 63-64), wherein a portion of the semiconductor element extends into a metal element (a contact structure 280) (Fig. 3G and paragraphs 102-104); and a dielectric material (an etch stop layer 190) on the portion of the semiconductor element contacts the metal element (190 is in direct contact with 280) (Fig. 3G and paragraphs 66-67).
Regarding claim 2, Chen teaches wherein the semiconductor element is a source/drain of a field-effect transistor (paragraphs 20 and 63-64).
Regarding claim 3, Chen teaches wherein the dielectric material on the portion of the semiconductor element is a spacer (190 spacing between 180 and 280) (Fig. 3G and paragraphs 66-67).
Regarding claim 5, Chen teaches wherein the field-effect transistor is at least one field-effect transistor of two vertically stacked field-effect transistors (two gate all around transistors shown in Fig. 3G).
Regarding claim 6, Chen teaches wherein each of the two vertically stacked field-effect transistors are a vertically stacked gate-all-around field-effect transistor, wherein each of the vertically stacked gate-all-around field-effect transistor have a sidewall of the source/drain covered by the dielectric material (a sidewall of 180 covered by 190) (Fig. 3G and paragraph 20).
Regarding claim 7, Chen teaches further comprising the metal element is at least one via (280) directly contacting the dielectric material (Fig. 3G, 280 is in direct contact with 190), and wherein the dielectric material electrically isolates the at least one via from the sidewall of the source/drain of each of the two vertically stacked gate-all-around field-effect transistors (190 electrically isolating/separating a portion of 180 covered by 190) (Fig. 3G).
Regarding claim 11, Chen teaches wherein the metal element is at least one element selected from the group of consisting a contact, a via, and a line (paragraphs 102-104), and wherein the semiconductor element is at least one element selected from the group consisting of a channel, a layer of a capacitor, a substrate, and a source/drain (paragraphs 63-65).
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2023/0065715 A1; hereinafter “Xie”).
Regarding claim 1, Xie teaches a semiconductor structure comprising: a semiconductor element (source and drain regions 710) of a semiconductor device (a gate-all-around transistor) (paragraphs 1-3 and 60), wherein a portion of the semiconductor element extends into a metal element (a metal S/D contact 1710 having conductive metal) (Fig. 17 and paragraph 73); and a dielectric material (a liner formed of TiN, not shown, having a dielectric constant about 5 is considered as “a dielectric material” since claim 1 requires neither the specific dielectric material choice nor the dielectric constant value of the dielectric material) on the portion of the semiconductor element contacts the metal element (the liner is between 710 and the conductive metal of 1710) (Fig. 17 and paragraph 73).
Regarding claim 2, Xie teaches wherein the semiconductor element is a source/drain of a field-effect transistor (paragraph 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 4, while Chen does not explicitly a thickness range in a numerical value for the dielectric material, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the dielectric material in a desired range, including the claimed thickness of 3-5 nm, as a routine experimentation for obtaining the optimal thickness for the dielectric material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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