DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claims 1-8 are objected to because of the following informalities:
In claim 1, line 11 and claim 6, line 16, “cavirty” should read –cavity--;
In claim 1, line 18, “postion” (two instances) should read –portion—or –position--, as may be appropriate.
In claim 6, penultimate line, “equivalanet” should read –equivalent--.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed first through fourth insulating resin layers and the substrate must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 requires the limitations “a substrate made of insulating resin, the substrate comprising … a second face” and “forming an electrical conductor such that the electrical conductor layer is embedded in the second face”. See lines 2-6. Referring to Fig. 1, the substrate is 11, and 12 is the seed layer on the first and second face. Fig. 5 shows electrical conductor layer 17. Clearly, the electrical conductor is not embedded in the second face. There is no support in the original application for the limitation “forming an electrical conductor such that the electrical conductor layer is embedded in the second face.”
Claim 6 requires the limitations “a substrate that is made of insulating resin, the substrate comprising … a second face”, “forming a second insulating resin on the second face; providing a seed layer on the second insulating resin layer; performing a pattern plating on a partial region of the seed layer to form an electrical conductor layer” and “forming a fourth insulating resin layer on the second insulating resin layer to embed the electrical conductor layer in at least the second face”. Referring to Fig. 1, the substrate is 11, and 12 is the seed layer on the first and second face. Fig. 5 shows electrical conductor layer 17. Clearly, the electrical conductor is not embedded in the second face. There is no support in the original application for the limitation “forming an electrical conductor such that the electrical conductor layer is embedded in the second face.” There is no support in the application as originally filed for the electrical conductor layer being embedded in the second face of the substrate.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, last line, the limitation “the electrical conductor layer embedded in the second insulating layer” lacks proper antecedent basis, as the claim refers at line 6 to the electrical conductor being embedded in the second face.
In claim 4, it is unclear what is meant by “continuously performed in order of nickel and copper”. Is the plating performed without stopping the plating process when switching metals, or what is meant by “continuously”? Similarly with respect to claim 5 limitation “continuously performed in order of nickel, gold, nickel and copper”.
In claim 6, line 13, the limitation “removing the insulating resin constituting the second insulating resin layer” renders the claim indefinite because it is unclear what is meant. As written, the limitation appears to suggest the entire
In claim 6, last line, the limitation “the electrical conductor layer embedded in the fourth insulating layer” lacks proper antecedent basis, as the claim refers at line 10 to the electrical conductor being embedded in the second face.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Furusawa (US2016/0113110A1) in view of Jiao (CN109219255A).
Furusawa discloses the claimed invention as follows:
Claim 1. A manufacturing method for a printed wiring board, the method comprising:
performing pattern plating (compare Figs. 3C and 3B; see [0067]) on a substrate (20z) made of insulating resin (see [0064]), the substrate comprising a first face (S) and a second face (F) located on a side opposite to the first face;
forming an electrical conductor layer (58F with 60FI) on a seed layer (34FI) provided on the second face (see Figs. 3C and 4B);
forming a first insulating resin layer (50S, Fig. 3D) on the first face and forming a second insulating resin layer (150F, Fig. 4C) such that the electrical conductor layer is embedded in the second face;
drilling (see “using a router” in [0085]) in a lamination direction from a side of the first insulating resin layer toward a partial region of the seed layer to penetrate the first insulating resin layer, and removing the insulating resin constituting the substrate (see Fig. 5B, 7D; see [0082])
wherein when forming the cavity, forming a side surface of the cavirty that extends linearly from the first face to the second face when the cavity is viewed in cross section (see Fig. 5B);
removing the partial region exposed at the bottom portion by flash etching (see Fig. 5C; see [0082]) to expose a postion of a surface of the second insulating resin layer to be equivalent to a postion of a surface of the electrical conductor layer embedded in the second insulating resin layer.
Claim 2. The manufacturing method for a printed wiring board according to claim 1, wherein in the drilling, the insulating resin is removed to a position that is located at a depth not less than 1/2 of a thickness of the substrate
Claim 3. The manufacturing method for a printed wiring board according to claim 1, further comprising: forming a via hole (28, Fig. 3B; see [0066] and [0067]) in a predetermined region of the substrate or of the second insulating resin layer; and performing pattern plating on the predetermined region comprising the via hole.
Claim 6. A manufacturing method for a printed wiring board, the method comprising:
forming
providing a seed layer (22F in Fig. 3B) on the second insulating resin layer;
performing pattern plating (see [0067] and Fig. 3D) on a partial region of the seed layer to form an electrical conductor layer (158F with 160F; see Fig. 4C);
drilling (see “using a router” in [0085]) in a lamination direction
wherein when forming the cavity, forming a side surface of the cavirty that extends linearly from the first face to the second face when the cavity is viewed in cross section (see Fig. 5B);
removing the partial region exposed at the bottom portion by flash etching (see Fig. 5C; see [0082]) to expose a position of a surface of the fourth insulating resin layer to be equivalanet to a position of a surface of the electrical conductor layer embedded in the fourth insulating resin layer.
Claim 7. The manufacturing method for a printed wiring board according to claim 6, wherein in the drilling, the insulating resin is removed to a position that is located at a depth not less than 1/2 of a thickness of the second insulating layer
Claim 8. The manufacturing method for a printed wiring board according to claim 6, further comprising:
forming a via hole (70F, Fig. 4A; see [0071]) in a predetermined region of the substrate or of the fourth insulating resin layer; and performing pattern plating (at 60F; see Fig. 4B and [0071]) on the predetermined region comprising the via hole.
Furusawa discloses the claimed invention, except for the drilling being such that the insulating resin is removed to a position that is located at a depth not less than 1/2 of a thickness of the substrate / second insulating layer, but that does not reach the partial region, the portion of the substrate / second insulating layer remaining at the bottom of the cavity being removed by laser machining.
Jiao teaches forming a cavity in a multilayer board by controlled-depth milling until only a thin layer of an insulating material remains at the bottom of the cavity (see Fig. 3 and [0046] and [0047]). Laser ablation is performed to remove the remaining insulating material (see Fig. 4 and [0048]). This process is used as an alternative to controlled-depth milling alone, “which is not only difficult to control the depth, making it hard to mill to the specified circuit layer and thus failing to meet design requirements” (see [0006]).
As mentioned above, Furusawa discloses forming cavity 26 using a router (e.g. deemed equivalent to drilling and milling, in this context). In view of the teachings of Jiao, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to mill the substrate / second insulating layer such that a portion of the substrate remains on the partial region inside the substrate, and utilizing a laser to remove the portion, for the same advantages taught by Jiao.
Regarding first and third insulating resin layers in claims 6-8, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the number of the layers defining the height of the cavity, as needed for a particular application, with predictable results.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Furusawa as modified in view of Jiao, further in view of Abe (US2006/0051895A1).
Modified Furusawa renders obvious the claimed invention, except for the limitations of claims 4 and 5. In [0033] and [0034] Furusawa discusses the bottoms of the vias, exposed to opening 26, being C4 pads. [0073] discusses forming a metal film on the portions of the pattern 34FI, these functioning as C4 pads. The metal film can be metal other than copper, such as gold, palladium, and tin. Nickel can also be formed between the metal film and a C4 pad. However, the description in Furusawa is not very clear regarding the order of layers.
Abe discloses an invention very similar to that of Furusawa and the claimed invention, wherein a substrate 10 (Fig. 1B) has a metal spacer 12 (e.g. copper foil; see [0032]) on one surface. On this spacer, a pattern plating process is used to form pads 21, which are functionally equivalent to the bottoms of the vias discussed by Fukusawa as being C4 pads (see Figs. 7C and 8A). An insulating layer 22 is disposed over the spacer and the pads, and via holes are filled with conductive material, as show in Fig. 3A-3C. See [0038] to [0040]. In forming the pads 21, Ni, Au, Ni and Cu are successively deposited in openings 41a. See Fig. 1D and [0034], the first nickel layer acting as a diffusion barrier.
Taking into consideration the teachings of Abe, and the fact that Furusawa already mentions Au and Ni layers in forming the pad portion at the bottom of the vias 60FI, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to successively plate Ni/Au/Ni/Cu in forming the metal film defining the C4 pad, discussed by Furusawa, since Abe shows it is conventional to use such a metal film arrangement in defining a pad portion to which a component with solder balls is to be attached. Compare Figs. 8A of Abe and 2A of Furusawa. Note that the order Ni/Au/Ni/Cu (claim 5) comprises the order Ni/Cu (claim 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US2016/0081182A1 discloses a process in which a portion 112 of a substrate is removed, leaving a metal layer 115 (see Fig. 20) covering an electrical conductor layer (140) during removal of the portion 112. Later 115 is then removed.
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
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