DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: STACKED FIELD-EFFECT TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME.
Claim Objections
Claim 10 objected to because of the following informalities: claim 10 depends on claim 13 and claim 13 is a device claim. Therefore, the examiner suggests changing to “10. The semiconductor device according to claim 13”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, and 10-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US Patent Appl. Pub. No. 2023/0142226 A1).
[Re claim 1] Xie discloses the method for manufacturing a semiconductor device, comprising: providing a substrate (202); forming a first field-effect transistor (2655) disposed on a substrate and a first isolation layer (1902) disposed on the first field-effect transistor, wherein a first through hole (lower portion of the cavity of 2806) runs through the first isolation layer, and a first metal layer (lower portion of the source/drain contact 2806) deposited in the first through hole is electrically connected to a source or a drain (1710) of the first field-effect transistor; forming a second isolation layer (2002) disposed on the first isolation layer; and forming a second field-effect transistor (2650) disposed on the second isolation layer; wherein a second through hole (upper portion of the cavity of 2806) runs in the second field-effect transistor and the second isolation layer, and a second metal layer (upper portion of the source/drain contact 2806) filled in the second through hole is electrically connected to the first metal layer and connected to a source or a drain (2202) of the second field-effect transistor (see x-x cross-sectional view) (see figure 18-28 and paragraph [0075]-[0087]).
[Re claim 2] Xie discloses the method wherein forming the first field-effect transistor disposed on the substrate and the first isolation layer disposed on the first field-effect transistor comprises: forming stacking layers on the substrate, wherein the stacking layers comprise at least one first semiconductor layer (210) and at least one second semiconductor layer (212) which are alternately stacked; etching the stacking layers to form a fin (see figure 17-18 and paragraph [0074]); forming a dummy gate (1708) on a portion of the fin, where in the dummy gate extends across the fin; forming the source and the drain at two sides, respectively, of the fin along a first direction (see figure 18 and paragraph [0075]-[0076]); removing the dummy gate (1708) and the at least one first semiconductor layer (210) to release the at least one second semiconductor layer as a channel (see figure 24 and paragraph [0083]); and forming a gate (2602) stack surrounding the channel (see figure 26 and paragraph [0085]).
[Re claim 6] Xie discloses the method wherein after forming the source and the drain (1710) at two sides of the fin along the first direction, the method further comprises: forming a third isolation layer (1720) on the source and the drain (see figure 18), wherein a third through hole (lower portion of the cavity of 2806 in isolation layer 1720) runs through the third isolation layer, and a third metal layer (lower portion of 2806 in isolation layer 1720) filled in the third through hole is configured to connect the first metal layer with the source or the drain electrically (see figure 28 and paragraph [0087]).
[Re claim 10] Xie discloses the device wherein the first metal layer (lower portion of the source/drain contact 2806) comprises only a single layer or comprises a plurality of layers (see figure 28).
[Re claim 11] Xie discloses the method wherein the first field-effect transistor and the second field-effect transistor each is a nanosheet gate-all-around field-effect transistor (see paragraph [0068]).
[Re claim 12] Xie discloses the semiconductor device, comprising: a substrate; a first field-effect transistor disposed on a substrate (202); a first isolation layer (1902) disposed on the first field-effect transistor (2655), wherein a first through hole (lower portion of the cavity of 2806) runs through the first isolation layer, and a first metal layer (lower portion of the source/drain contact 2806) deposited in the first through hole is electrically connected to a source or a drain (1710) of the first field-effect transistor; a second isolation layer (2002) disposed on the first isolation layer; and a second field-effect transistor (2650) disposed on the second isolation layer; wherein a second through hole (upper portion of the cavity of 2806) runs in the second field-effect transistor and the second isolation layer, and a second metal layer (upper portion of the source/drain contact 2806) filled in the second through hole is electrically connected to the first metal layer and connected to a source or a drain of the second field-effect transistor (see x-x cross-sectional view) (see figure 18-28 and paragraph [0075]-[0087]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Patent Appl. Pub. No. 2023/0142226 A1) in view of Cheng et al. (US Patent Appl. Pub. No. 2023/0187551 A1).
[Re claim 8 and 13] Xie discloses the method and device as claimed and rejected in claim 1 and 12, but Xie does not disclose method or device wherein a material of the first metal layer comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag. Cheng discloses the method and device wherein a material of the first metal layer (191) comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag (see figure 1 and paragraph [0103]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to the first metal layer comprises at least one of W, Al, Cu, Co, Ti, Pt, TiN, TaN, TiC, Mo, Ru, Au, or Ag in the method of Xie in order to form better electrically conductive contact layer.
Claim(s) 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Patent Appl. Pub. No. 2023/0142226 A1).
[Re claim 9 and 14] Xie fails to disclose the selection of “a thickness or a width of the first metal layer ranges from 1nm to 10000nm”. However, it would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claim 3-5 and 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817