DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a first communication circuit” and “a second communication circuit”, each of which also include “an amplifier”. It is unclear whether the “amplifier” of the first communication circuit and the second communication circuit are different amplifiers or the same amplifier. The current claim language appears to distinguish different entities of the same kind by using “first” or “second”, e.g. “first signal input” and “second signal input”. However, the “amplifier” in the first communication circuit are not distinguished using “first” or “second”. In addition, claim 1 recites that the second communication circuits having (iii) a second control output configured for signaling when the amplifier coupled between the signal output and the signal input is to be active” in lines 14-15. Since the claim recites “a first signal input”, “a second signal input”, “a first signal output”, and “a second signal output”, it is unclear which signal input/output is being referred to when the claim simply recites “the signal output and the signal input” in lines 14-15. Therefore, the scope of the claim is indefinite with regards to “the amplifier” and “the signal output and the signal input”.
Claim 8 contain similar issues as claim 1 and is rejected for the same reasoning as shown above.
Claim 2 recites “wherein the first and second devices comprise a clock external to the first and second communication circuits, and the system is configured to synchronize the clocks in dependence on the timings of signals at the first and second control outputs”. The claim recites a singular clock followed by the recitation of “the clocks” (plural). The recitation of “the clocks” therefore lack antecedent basis. In addition, it is unclear whether the first and second devices each comprise a separate clock external to the first and second communication circuits or the first and second device comprise a single clock that is external to the first and the second communication circuits. Therefore, the scope of claim 2 is unclear and “the clocks” recited in claim 2 lacks antecedent basis as currently presented.
Claim 9 contain similar issues as claim 2 and is rejected for the same reasoning as shown above.
Claim 6 recites “wherein the system is configured to synchronise the clock in dependence on the timing of the first signal output only if it detects the second signal output within a predetermined time after the first output signal”. Claim 6 is dependent on claim 2, which is unclear as shown above whether claim 2 recites a single clock or multiple clocks. Claim 6 is also dependent on claim 3, which appears to further require claim 2 to include multiple clocks. Therefore, it would be unclear which clock of the multiple clocks is being synchronized in claim 6. The scope of claim 6 is therefore unclear and rejected herein.
Claims 10, 12 and 14 recites “the integrated circuit” (singular). However, the parent claim 8 recites two devices each having an integrated circuit. Therefore, there are two integrated circuits recited in claim 8 such that it is unclear which of the two integrated circuits is being referred to by “the integrated circuit in claims 10, 12 and 14. The scopes of claims 10, 12 and 14 are therefore indefinite and rejected herein.
Claims 2-7 and 9-14 are rejected as each of these claims are dependent on the above rejected claims 1 or 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 8-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang (US 2017/0188264).
Hwang discloses the following features.
Regarding claim 1, a system for synchronizing two devices (see system shown in Fig. 1 including transmitter chain 113 and receiver chain 115; paragraph [0018] and Fig. 3 shows synchronization between the receiver chain and transmitter chain being performed in order to cancel aggressor signal from the transmitter chain):
a first device (see transmitter chain 113 in Fig. 1) comprising:
a first communication circuit (see transmitter chain 113 and transmitter antenna 102 in Fig. 1) implemented as an integrated circuit, having (i) a first signal output configured for presenting a signal for transmission to an amplifier (see mixer 110 and distributed amplifier 112 in Fig. 1 for presenting signal for transmission to the power amplifier 114), (ii) a first signal input configured for receiving a signal for transmission from the amplifier (see Tx filter 116 in Fig. 1 for receiving signal for transmission using the transmitter antenna 112 from the power amplifier 114), and (iii) a first control output configured for signaling when the amplifier coupled between the first signal output and the first signal input is to be active (see “transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof)” recited in paragraph [0049]); and
a second device (see receiver chain 115, receiver antenna 103 and AIC component 140 for receiving and processing the received signals in Fig. 1) comprising:
a second communication circuit (see receiver chain 115 and receiver antenna 103 in Fig. 1) implemented as an integrated circuit, having (i) a second signal output configured for presenting a signal for transmission to an amplifier (see summer 120 presenting signal for transmission to the low-noise amplifier 124 in Fig. 1), (ii) a second signal input configured for receiving an amplified signal signal for transmission from the amplifier (see analog filter 126 in Fig. 1 for receiving signal to be processed using from the low-noise amplifier 124), with the second communication circuit being configured to perform signal decoding on a signal received at the signal input (see ADC and digital filter 132 in Fig. 1 and paragraph [0026] “to produce a digital received signal 133 for providing to transceiver for processing at higher network layers”), and
and (iii) a second control output configured for signaling when the amplifier coupled between the signal output and the signal input is to be active (see “control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna” recited in paragraph [0049], wherein the low-noise amplifier 124 being part of the receiver chain controlled by the control I/O);
wherein the system is configured to determine a relative timings of events sensed by the first and second devices in dependence on the timings of the signals at the first and second control output (see “synchronizing a clock of the analog interference cancellation component with a different clock of the transmitter chain based at least in part on a time period or detected event… in an example, the detected event may include… transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof), control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna, etc.” recited in paragraph [0049]; also see paragraph [0048], wherein timestamps are used for the synchronization, wherein the timestamps represents relative timing of events).
Regarding claim 2, wherein the first and second devices comprise a clock external to the first and second communication circuits (see “clock of processor(s) 105” recited in paragraph [0049], wherein the processor is external to the receive transmitter chain 113 and the receive chain 115 as shown in Fig. 1), and the system is configured to synchronize the clocks in dependence on the timings of signals at the first and second control outputs (see “Where the transmitter chain 113 and AIC component 140 utilize different clocks, however, periodic or event driven synchronization of the clocks may be desired” recited in paragraph [0049]).
Regarding claim 3, wherein the system is configured to time a first event at the first device with reference to its clock and time a second event at the second device by reference to its clock (see paragraph [0049] and Fig. 3, which shows that “the transmitter chain 113 and AIC component 140 utilize different clocks” and performs the synchronization based on detected event, wherein the transmitter chain 113 and AIC component 140 each has its own clock and must time the events, e.g. the synchronizing steps 302-306 in Fig. 3 using its own clock).
Regarding claim 4, wherein the system is configured to provide the second signal output for indicating that the events are logically complete (see “he detected event may include a coexistence manager (CxM) (e.g., to reduce the interference to the receiver using transmit signal power backoff, time coordination between the transmitter chain 113 and the receiver chain 115, and/or transmit signal blanking), time boundary indication (e.g., as given from a PA, such as PA 114, in the transmitter chain 113 or baseband so the receiver chain 115 may acknowledge the timing of aggressor signal's uplink transmission cycle, e.g., ON duration), transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof), control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna, etc.” recited in paragraph [0049], wherein the time boundary indication and the control I/O may be considered as timing at which a communication event is logically complete).
Regarding claim 5, wherein the second signal output is provided as an interrupt (see “interrupt” recited in paragraph [0049]).
Regarding claim 8, a method for synchronizing two devices (see system shown in Fig. 1 including transmitter chain 113 and receiver chain 115; paragraph [0018] and Fig. 3 shows synchronization between the receiver chain and transmitter chain being performed in order to cancel aggressor signal from the transmitter chain), each device having a communication circuit implemented as an integrated circuit, a first one of the communication circuits (see transmitter chain 113 and transmitter antenna 102 in Fig. 1) having (i) a first signal output configured for presenting a signal for transmission to an amplifier (see mixer 110 and distributed amplifier 112 in Fig. 1 for presenting signal for transmission to the power amplifier 114), (ii) a first signal input configured for receiving a signal for transmission from the amplifier (see Tx filter 116 in Fig. 1 for receiving signal for transmission using the transmitter antenna 112 from the power amplifier 114), and (iii) a first control output configured for signaling when the amplifier coupled between the first signal output and the first signal input is to be active (see “transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof)” recited in paragraph [0049]); and a second one of the communication circuits (see receiver chain 115, receiver antenna 103 and AIC component 140 for receiving and processing the received signals in Fig. 1) having (i) a second signal output configured for presenting a signal for transmission to an amplifier (see summer 120 presenting signal for transmission to the low-noise amplifier 124 in Fig. 1), (ii) a second signal input configured for receiving an amplified signal for transmission from the amplifier (see analog filter 126 in Fig. 1 for receiving signal to be processed using from the low-noise amplifier 124), with the second communication circuit being configured to perform signal decoding on a signal received at the signal input (see ADC and digital filter 132 in Fig. 1 and paragraph [0026] “to produce a digital received signal 133 for providing to transceiver for processing at higher network layers”), and (iii) a second control output configured for signaling when the amplifier coupled between the signal output and the signal input is to be active (see “control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna” recited in paragraph [0049], wherein the low-noise amplifier 124 being part of the receiver chain controlled by the control I/O); the method comprising determining a relative timings of events sensed by the first and second devices in dependence on the timings of the signals at the first and second control output (see “synchronizing a clock of the analog interference cancellation component with a different clock of the transmitter chain based at least in part on a time period or detected event… in an example, the detected event may include… transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof), control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna, etc.” recited in paragraph [0049]; also see paragraph [0048], wherein timestamps are used for the synchronization, wherein the timestamps represents relative timing of events).
Regarding claim 9, wherein each device comprises a clock external to the communication circuit (see “clock of processor(s) 105” recited in paragraph [0049], wherein the processor is external to the receive transmitter chain 113 and the receive chain 115 as shown in Fig. 1), and the method comprises synchronizing the clocks in dependence on the timings of signals at the first and second control outputs (see “Where the transmitter chain 113 and AIC component 140 utilize different clocks, however, periodic or event driven synchronization of the clocks may be desired” recited in paragraph [0049]).
Regarding claim 10, timing a first event at the first device with reference to its clock and time a second event at the second device by reference to its clock (see paragraph [0049] and Fig. 3, which shows that “the transmitter chain 113 and AIC component 140 utilize different clocks” and performs the synchronization based on detected event, wherein the transmitter chain 113 and AIC component 140 each has its own clock and must time the events, e.g. the synchronizing steps 302-306 in Fig. 3 using its own clock).
Regarding claim 11, wherein the integrated circuit is configured to provide the second signal output for indicating that the events are logically complete (see “he detected event may include a coexistence manager (CxM) (e.g., to reduce the interference to the receiver using transmit signal power backoff, time coordination between the transmitter chain 113 and the receiver chain 115, and/or transmit signal blanking), time boundary indication (e.g., as given from a PA, such as PA 114, in the transmitter chain 113 or baseband so the receiver chain 115 may acknowledge the timing of aggressor signal's uplink transmission cycle, e.g., ON duration), transmit/receive indication control I/O signal for an external PA (e.g., PA 114, which may indicate activation thereof), control I/O for a switch where the transmitter chain 113 and the receiver chain 115 use a shared antenna, etc.” recited in paragraph [0049], wherein the time boundary indication and the control I/O may be considered as timing at which a communication event is logically complete).
Regarding claim 12, wherein the second signal output is provided as an interrupt (see “interrupt” recited in paragraph [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang as applied to claims 1 and 8 above, and further in view of Abedini (US 2015/0117437).
Hwang discloses the features as shown above.
Hwang also disclose the following features.
Regarding claims 7 and 14, wherein the system operates according to a protocol that provides for a synchronization signal to be transmitted at a predetermined time by one participant in a network and wherein the event is the transmission or reception of such a signal (see “Where the synchronization is based on a detected event, for example, the event may be specified in a configuration from the network entity 170” recited in paragraph [0049]).
Hwang does not disclose the following features: regarding claims 7 and 14, wherein the synchronization signal is to be received by all other participants in the network.
Abedini discloses the following features.
Regarding claims 7 and 14, wherein the synchronization signal is to be received by all other participants in the network (see “eNBs may broadcast synchronization signals (PSS/SSS) in each cell” recited in paragraph [0026]).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the current Application to modify the system of Hwang using features, as taught by Abedini, in order to achieve synchronization for devices within a network (see paragraph [0026] of Abedini).
Allowable Subject Matter
Claims 6 and 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUTAI KAO whose telephone number is (571)272-9719. The examiner can normally be reached Monday-Friday 8:00-17:00 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kwang Yao can be reached at (571)272-3182. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUTAI KAO/Primary Examiner, Art Unit 2473
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