DETAILED ACTION
This Office Action is in response to the application filed on 18 December 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,888,043 (hereinafter ‘043). Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, Claim 1 of ‘043 teaches, verbatim, an integrated circuit structure, comprising:
a fin;
a gate structure over the fin, the gate structure including a recessed conductive portion and a non-recessed conductive portion;
an insulating layer on the recessed conductive portion of the gate structure and laterally adjacent to the non-recessed conductive portion of the gate structure, wherein the insulating layer has an uppermost surface at a same level as an uppermost surface of the non-recessed conductive portion of the gate structure; and
a conductive trench contact structure laterally adjacent to the gate structure, the conductive trench contact structure.
Claim 1 of ‘043 appears to be silent as to the limitations of the non-recessed conductive portion having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface at a same level as the uppermost surface of the insulating layer; however the disclosure of ‘043 teaches a non-recessed conductive portion (564/660) having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface (top) at a same level as the uppermost surface of the insulating layer (top surface of an insulating layer) (fig. 6E). Therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to incorporate the teachings of ‘043 into the claims of ‘043 to have the limitations in question.
In regards to claim 2, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 1. Claim 5 of ‘043 further teaches the limitations wherein the insulating layer comprise silicon nitride (wherein the trench insulating layer comprises silicon carbide, and the insulating layer comprise silicon nitride).
In regards to claim 3, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 1. Claim 6 of ‘043 further teaches the limitations further comprising: a dielectric spacer laterally between the conductive trench contact structure and the gate structure (a dielectric spacer laterally between the conductive trench contact structure and the gate structure).
In regards to claim 4, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 1. Claim 1 of ‘043 further teaches, verbatim, the limitations further comprising:
an interlayer dielectric material above the gate structure and the conductive trench contact;
an opening in the interlayer dielectric material, the opening exposing the non-recessed conductive portion of the gate structure; and
a conductive structure in the opening, the conductive structure in direct contact with the non-recessed conductive portion of the gate structure.
In regards to claim 5, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 4. Claim 2 of ‘043 further teaches, verbatim, the limitations wherein the opening further exposes a portion of the insulating layer.
In regards to claim 6, Claim 7 of ‘043 teaches, verbatim, an integrated circuit structure, comprising:
a three-dimensional body;
a gate structure completely surrounding a channel region of the three-dimensional body, the gate structure including a recessed conductive portion and a non-recessed conductive portion;
an insulating layer on the recessed conductive portion of the gate structure and laterally adjacent to the first side and the second side of non-recessed conductive portion of the gate structure, wherein the insulating layer has an uppermost surface at a same level as an uppermost surface of the non-recessed conductive portion of the gate structure;
a conductive trench contact structure laterally adjacent to the gate structure, the conductive trench.
Claim 7 of ‘043 appears to be silent as to the limitations of the non-recessed conductive portion having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface at a same level as the uppermost surface of the insulating layer; however the disclosure of ‘043 teaches a non-recessed conductive portion (564/660) having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface (top) at a same level as the uppermost surface of the insulating layer (top surface of an insulating layer) (fig. 6E). Therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to incorporate the teachings of ‘043 into the claims of ‘043 to have the limitations in question.
In regards to claim 7, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 6. Claim 11 of ‘043 further teaches the limitations wherein the insulating layer comprise silicon nitride (wherein the trench insulating layer comprises silicon carbide, and the insulating layer comprise silicon nitride).
In regards to claim 8, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 6. Claim 12 of ‘043 further teaches, verbatim, the limitations further comprising: a dielectric spacer laterally between the conductive trench contact structure and the gate structure.
In regards to claim 9, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 6. Claim 7 of ‘043 further teaches, verbatim, the limitations further comprising:
an interlayer dielectric material above the gate structure and the conductive trench contact;
an opening in the interlayer dielectric material, the opening exposing the non-recessed conductive portion of the gate structure; and
a conductive structure in the opening, the conductive structure in direct contact with the non-recessed conductive portion of the gate structure.
In regards to claim 10, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 9. Claim 2 of ‘043 further teaches, verbatim, the limitations wherein the opening further exposes a portion of the insulating layer.
In regards to claim 11, Claim 13 of ‘043 teaches, verbatim, a computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin;
a gate structure over the fin;
the gate structure including a recessed conductive portion and a non-recessed conductive portion;
an insulating layer on the recessed conductive portion of the gate structure and laterally adjacent to the non-recessed conductive portion of the gate structure, wherein the insulating layer has an uppermost surface at a same level as an uppermost surface of the non-recessed conductive portion of the gate structure; and
a conductive trench contact structure laterally adjacent to the gate structure.
Claim 13 of ‘043 appears to be silent as to the limitations of the non-recessed conductive portion having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface at a same level as the uppermost surface of the insulating layer; however the disclosure of ‘043 teaches a non-recessed conductive portion (564/660) having a first side and a second side the second side laterally opposite the first side; and having an uppermost surface (top) at a same level as the uppermost surface of the insulating layer (top surface of an insulating layer) (fig. 6E). Therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to incorporate the teachings of ‘043 into the claims of ‘043 to have the limitations in question.
The combination of the disclosure of ‘043 and Claim 13 appear to be silent as to the limitations of a three-dimensional body; and a gate structure completely surrounding a channel region of the three-dimensional body; however, Claim 17 of ‘043 teach these limitations verbatim. Therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to combine the teaches of the claims of ‘043 to have the limitations in question.
In regards to claim 12, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Claim 13 of ‘043 further teaches, verbatim, the limitation comprising the fin.
In regards to claim 13, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Claim 17 of ‘043 further teaches, verbatim, the limitation comprising the three-dimensional body.
In regards to claim 14, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Claim 14 of ‘043 further teaches, verbatim, the limitation comprising a memory coupled to the board.
In regards to claim 15, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Claim 15 of ‘043 further teaches, verbatim, the limitation comprising a communication chip coupled to the board.
In regards to claim 16, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Fig. 11 and paragraph [00138] of ‘043 further teaches a battery coupled to the board.
In regards to claim 17, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Fig. 9 and paragraph [00128] of ‘043 further teaches a camera coupled to the board.
In regards to claim 18, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Fig. 11 and paragraph [00138] of ‘043 further teaches a display coupled to the board.
In regards to claim 19, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Claim 16 of ‘043 further teaches, verbatim, the limitations wherein the component is a packaged integrated circuit die.
In regards to claim 20, the combination of the disclosure of ‘043 teaches the limitations discussed above in addressing claim 11. Fig. 11 and paragraph [00138] of ‘043 further teaches the limitations wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812