Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The following is a final office action in response to the communication filed on 07/16/2026. Claims 1-6 have been amended. The prior art of the previous office action is still relied upon and is used to teach the limitations added by applicant’s amendment.
Response to Arguments
Applicant's arguments filed 07/16/2026 have been fully considered but they are not persuasive. Applicant argues quote “However, in the context of the present application, the “first and second timings” as claimed do not correspond to Stp1 and Stp2. Rather, they correspond to Stp and Stp’ as described in paragraph [0046] of the present application (emphasis added):” and proceeds to insert quote from applicants specification. While the claims are viewed in light of the specification the limitations of the specification are not brought into the claims. The prior art does teach the limitation of the first and second timings as explained below. Applicant also argues that claim 4 is not taught by the prior art for the same reasoning. The prior art does not have to teach the same reasonings as the claimed invention for the prior art to read on the claimed limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohnaka et al. (EP 3875986 A1).
Regarding claim 1, Ohnaka teaches
A sensor device comprising: (FIG. 1 is a block diagram illustrating a configuration of a sensor device 100 according to an embodiment (paragraph 0036 and fig. 1))
a light emitter configured to emit detection light toward a target; (As illustrated in FIG. 1, the sensor device 100 includes a light emitting unit 10 (paragraph 0037 and fig. 1))
a light receiver configured to receive reflected light of the detection light and generate a binarization signal; (The light receiving unit 20 is configured to receive reflected light of the detection light and generate a binarized signal RT. (paragraph 0040))
a counter measurer configured to generate first and second timings on a basis of the binarization signal; (As illustrated in FIG. 3, the counter measurement unit 32 starts counting of the binarized signals RT in response to the start signal St. The counting of the binarized signals RT is performed based on the clock signal Ck input from the PLL 47. In addition, the counter measurement unit 32 generates stop signals Stp1, Stp2, Stp3, and Stp4 (hereinafter, collectively referred to as the "stop signals Stp") (paragraph 0057 and fig. 3))
a delay line configured to receive and propagate the binarization signal; (Moreover, FIG. 3 illustrates an example in which the TDC delay line measurement unit 33 is configured of four TDC delay lines; however, the configuration of the TDC delay line measurement unit is not limited thereto. The TDC delay line measurement unit 33 may have an increase or a decrease in TDC delay lines, depending on a size of logic capacity. (paragraph 0058 and fig. 3))
first and second memories configured to record binarization signals propagated through the delay line on a basis of the first and second timings, respectively, the binarization signals each being the binarization signal; (The first TDC delay line 301 has delay elements 6-1, 6-2, 6-3, ···, and 6-n (n is a positive integer) (hereinafter, collectively referred to as the "delay element 6") and flip-flop circuits 7-1, 7-2, 7-3, ···, and 7-n (hereinafter, collectively referred to as the "flip-flop circuit 7"). (paragraph 0059))
an integrator configured to generate first and second sets of integrated waveform data by integrating the binarization signals recorded in the first and second memories, respectively, corresponding to a plurality of times of light emission in the light emitter; (The waveform integration unit 34 integrates the delay line output signals D1 to D4 input from the TDC delay line measurement unit 33 a plurality of times and generates an integration signal Dt. (paragraph 0046))
a distance converter configured to calculate a measured distance value to the target on a basis of the first set of integrated waveform data and the second set of integrated waveform data, wherein the first set of integrated waveform data is processed to derive a first distance and the second set of integrated waveform data is processed to derive a second distance, and the measured distance value is calculated based on the first distance and the second distance; (The distance calculation step may include calculating the first distance value and the second distance value from the respective intersections of the first integration threshold value and the second integration threshold value with the second integrated waveform data (paragraph 0027) The distance conversion unit 38 converts the number of stages of the delay circuits which is input from the stage number calculation unit 37 into a distance from the sensor device 100 and outputs the converted distance. (paragraph 0050))
and a determiner configured to determine presence or absence of the target on a basis of the measured distance value. (In addition, the controller 50 includes a determination unit 51 as a functional configuration of the controller. The determination unit 51 determines presence or absence of the target object TA at a predetermined distance as illustrated in FIG. 2, that is, presence or absence of the target object TA, on the basis of the output result of the distance conversion unit 38 which is included in the measured signal T1 input from the interface unit 41. (paragraph 0054 and fig. 2))
Regarding claim 2, Ohnaka teaches
The sensor device according to claim 1, wherein the distance converter calculates the measured distance value to the target, using one of the first and second sets of integrated waveform data according to a predetermined measurement section. (The distance conversion unit 38 converts the number of stages of the delay circuits which is input from the stage number calculation unit 37 into a distance from the sensor device 100 and outputs the converted distance. (paragraph 0050))
Regarding claim 3, Ohnaka teaches
The sensor device according to claim 1, wherein the distance converter calculates the measured distance value to the target by combining and computing at least two or more of the first and second sets of integrated waveform data in a specific measurement section. (The counter measurement unit 32 performs sampling of binarized information of the binarized signal RT with the sampling signal Smp based on the clock signal, within the measurement section M1. (paragraph 0068) A counter integration signal Cn is a signal obtained by measuring the binarized information of the binarized signal RT with the sampling signal Smp to the predetermined number of times (n times) of integration and integrating the binarized information obtained by n times of integration for each clock. (paragraph 0069))
Regarding claim 5, Ohnaka teaches
The sensor device according to claim 1, wherein the counter measurer generates the first timing on a basis of a feature point of the binarization signal, and generates a second timing from the first timing on a basis of a clock signal. (The counter measurement unit 32 generates a stop signal Stp corresponding to a characteristic point of the binarized signal RT (paragraph 0044 and fig. 3 and 7) It can be seen by figures 3 and 7 that the second timing is generated from a first timing that is a clock signal.)
Regarding claim 6, Ohnaka teaches
The sensor device according to claim 5, wherein the second timing is one clock later than the first timing. ((fig. 7) Figure 7 shows the second timing being one clock later than the first timing)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ohnaka et al.(EP3875986 A1) in view of Ohnaka et al. (EP 3680683 A1). [To differentiate which reference is being addressed since they both have the same inventor the second reference will be referred to by there first name Shoichi.]
Regarding claim 4 Ohnaka teaches all of the elements of claim 3 as previously stated, however Ohnaka fails to teach wherein the distance converter (38) calculates the measured distance value to the target by performing a weighted average process on the first and second sets of integrated waveform data in a specific section.
In the same field of endeavor, Shoichi teaches wherein the distance converter (38) calculates the measured distance value to the target by performing a weighted average process on the first and second sets of integrated waveform data in a specific section. (referably, the distance calculation unit performs filter processing on the second integrated waveform data by a simple moving average or a weighted moving average, before calculating the distance to the object. (paragraph 0015))
It would have been obvious to someone with ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features disclosed in Shoichi into the invention of Ohnaka. Both references are considered analogous arts to the claimed invention as they both disclose distance measurement sensors. The combination of Ohnaka and Shoichi would increase the accuracy of the distance measurement.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN J SLAUGHTER whose telephone number is (571)388-3021. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vladimir Magloire can be reached at (571) 270-5144. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ETHAN JAKOB SLAUGHTER/Examiner, Art Unit 3648
/VLADIMIR MAGLOIRE/Supervisory Patent Examiner, Art Unit 3648
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