DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-15 are objected to because of the following informalities:
In claim 1, lines 22 and 24, after both “a first external electrode layer” and “a second external electrode layer” the term --extends-- is missing. The claim in part should read “a first external electrode layer extends from the first electrode through a first side surface of the substrate to the third electrode” (from paragraph 0038 in the current specification).
In claim 11, lines 22 and 24, after “a first external electrode layer” and “a second external electrode layer” the term --extends-- is missing.
Claims 2-10 and 12-15 depend on claims 1 and 11, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoneda.
Regarding claim 11, Yoneda teaches chip resistor (“chip resistor”; see at least col. 3, lines 44-65 and fig. 1), comprising:
a substrate (alumina substrate 1) comprising a front surface and a back surface, wherein the front surface comprises a first edge area and a second edge area opposite to
each other;
a first electrode and a second electrode (upper surface electrodes 21 and 31) respectively disposed on a portion of the first edge area and a portion of the second edge area;
a resistance layer (resistor body 4) disposed on the front surface and extending from the
first electrode to the second electrode;
a first insulating protective layer (protective layer 52) completely covering the resistance layer (4);
a resin electrode layer (electrodes 24 and 34 made of resin paste and silver; col. 5, lines 5-10), wherein the resin electrode layer comprises:
a first portion (24) covering the first electrode (21) and a portion of the first
insulating protective layer (52) adjacent to the first electrode; and
a second portion (34) covering the second electrode (31) and a portion of
the first insulating protective layer (52) adjacent to the second electrode, wherein the second portion and the first portion are separated from each other (see fig. 1);
a second insulating protective layer (53) covering the first insulating protective
layer (52) between the first portion and the second portion and partially covering the first portion (24) and the second portion (34);
a third electrode and a fourth electrode (shorter lower electrodes below the electrodes 22 and 32) disposed on the back surface and opposite to the first electrode and the second electrode respectively;
a first external electrode layer (layers 35a and 35b) extends from the first electrode through a first side surface of the substrate to the third electrode; and
a second external electrode layer (layers 35a and 35b) from the second electrode through a second side surface of the substrate to the fourth electrode.
Regarding claim 12, Yoneda teaches the chip resistor of claim 11, wherein each of the first electrode and the second electrode comprises a first section, a second section, and a third
section, the first section and the second section are respectively connected to two opposite ends of the third section and protrude from the third section, and the third section of the first electrode and the third section of the second electrode respectively extend along one side of the first side surface and one side of the second side surface, wherein the first electrode has a C-like structure, and the second electrode has an inverted C-like structure (see the reproduced fig. 1 below).
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501
624
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Greyscale
Allowable Subject Matter
Claims 1-10 are allowed.
Prior art does not teach or suggest a chip resistor having “a third portion covering a portion of the first insulating protective layer which is on the resistance layer, wherein the first portion, the second portion, and the third portion are separated from each other; and
a second insulating protective layer completely covering the third portion
and partially covering the first portion and the second portion.”
Claims 2-10 depend on claim 1.
Claims 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, the prior art does not teach or suggest the chip resistor, wherein each of the first sections and the second sections has a length greater than 50 µm and smaller than 250 µm, and each of the third sections has a length greater than 50 µm and smaller than 150 µm.
Regarding claim 14, the prior art does not teach or suggest the chip resistor, wherein each of the first electrode and the second electrode is a rectangular structure, the first electrode and the second electrode extend toward the second edge area and the first edge area respectively, and each of the first electrode and the second electrode has a length greater than 50 µm and smaller than 250 µm, and a width greater than 50 µm and smaller than 200 µm.
Claim 15 depends on claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F.
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/KYUNG S LEE/Primary Examiner, Art Unit 2831
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