DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawing objections as previously issued have been withdrawn due to Applicant’s amendments dated July 20th, 2026.
Specification
The specification objection as previously issued has been withdrawn due to Applicant’s amendments dated July 20th, 2026.
Claim Rejections - 35 USC § 112
The 35 USC § 112(b) rejection as previously issued has been withdrawn due to Applicant’s amendments dated July 20th, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, 16, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando, et al. (US 10879308 B1; hereinafter referred to as Ando).
Regarding Claim 1, Ando discloses a method for forming a semiconductor device, comprising:
forming a device structure (FET stacks 402, 404, 406, Col. 6, lines 45-49, Fig. 9) on a substrate (substrate 302, Col. 5, lines 24-25), the device structure comprising:
a device layer stack (FET stack 406, Fig. 9) comprising:
a bottom device sub-stack (lower nanosheets, Fig. 9) comprising at least one bottom channel layer (channel Si nanosheets 308c, 312c, 316c, Fig. 9); and
a top device sub-stack (upper nanosheets, Fig. 9) comprising at least one top channel layer (channel Si nanosheets 320c, 324c, 328c, Fig. 9);
a sacrificial gate structure extending across the device layer stack (sacrificial gate structure 334, Col. 9, lines 30-41, Fig. 9); and
bottom source/drain structures on opposite ends of the at least one bottom channel layer (lower source and drains 502, Col. 7, lines 54-58, Fig. 9),
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forming an opening exposing the top device sub-stack (opening, see Annotated Fig. 10), wherein forming the opening comprises etching the sacrificial gate structure (Col. 9, lines 34-51);
forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening (cavity 1302, Col. 11, lines 10-15, Fig. 13), wherein the etching extends through each of the at least one top channel layer and is stopped over the bottom device sub-stack (Fig. 13), and wherein the cut is configured to prevent formation of an active top device during subsequent process steps (Fig. 13; the upper nanosheets are no longer active after the cut as the cut goes through the nanosheets); and
subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer (gate dielectric 1104 and gate conductor 1108 together form the functional gate stack, Col. 10-11, lines 66, lines 1-6).
Regarding Claim 5, Ando discloses the method according to claim 1, wherein the opening is formed to selectively expose a top surface portion of the device layer stack (Fig. 10, the opening is formed before the cut and, therefore, exposes a top surface portion of the device layer stack), and wherein portions of the sacrificial gate structure remain along sidewalls of the bottom device sub-stack and the top device sub-stack after forming the opening (Fig. 10, sacrificial gate spacers 335 remain immediately after the forming of the opening, which are part of the sacrificial gate stack).
Regarding Claim 7, Ando discloses the method according to claim 1, further comprising filling the opening in the sacrificial gate structure and the cut with a dielectric fill material (gate dielectric 1104, Fig. 11) and subsequently removing the sacrificial gate structure (Fig. 13).
Regarding Claim 16, Ando discloses a semiconductor device formed according to a method, the method comprising:
forming a device structure (FET stacks 402, 404, 406, Col. 6, lines 45-49, Fig. 9) on a substrate (substrate 302, Col. 5, lines 24-25), the device structure comprising:
a device layer stack (FET stack 406, Fig. 9) comprising:
a bottom device sub-stack (lower nanosheets, Fig. 9) comprising at least one bottom channel layer (channel Si nanosheets 308c, 312c, 316c, Fig. 9); and
a top device sub-stack (upper nanosheets, Fig. 9) comprising at least one top channel layer (channel Si nanosheets 320c, 324c, 328c, Fig. 9);
a sacrificial gate structure extending across the device layer stack (sacrificial gate structure 334, Col. 9, lines 30-41, Fig. 9); and
bottom source/drain structures on opposite ends of the at least one bottom channel layer (lower source and drains 502, Col. 7, lines 54-58, Fig. 9);
forming an opening exposing the top device sub-stack (opening, see Annotated Fig. 10), wherein forming the opening comprises etching the sacrificial gate structure (Col. 9, lines 34-51);
forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening (cavity 1302, Col. 11, lines 10-15, Fig. 13), wherein the etching extends through each of the at least one top channel layer and is stopped over the bottom device sub-stack (Fig. 13), and wherein the cut is configured to prevent formation of an active top device during subsequent process steps (Fig. 13; the upper nanosheets are no longer active after the cut as the cut goes through the nanosheets) and
subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer (gate dielectric 1104 and gate conductor 1108 together form the functional gate stack, Col. 10-11, lines 66, lines 1-6).
Regarding Claim 18, Ando discloses the semiconductor device according to claim 16, wherein the opening is formed to selectively expose a top surface portion of the device layer stack (Fig. 10, the opening is formed before the cut and, therefore, exposes a top surface portion of the device layer stack), and wherein portions of the sacrificial gate structure remain along sidewalls of the bottom device sub-stack and the top device sub-stack after forming the opening (Fig. 10, sacrificial gate spacers 335 remain immediately after the forming of the opening, which are part of the sacrificial gate stack).
Regarding Claim 19, Ando discloses the semiconductor device according to claim 16, wherein the method comprises filling the opening in the sacrificial gate structure and the cut with a dielectric fill material (gate dielectric 1104, Fig. 11) and subsequently removing the sacrificial gate structure (Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-4, 6, 8, 11-15, 17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ando as applied to claims 1, 5, 7, 16, and 18-19 above, and further in view of Yun, et al. (US 20230086084 A1; hereinafter referred to as Yun).
Regarding Claim 2, Ando discloses the method according to claim 1,
wherein the opening is formed to expose a top surface of the device layer stack and sidewalls of the bottom device sub-stack and the top device sub-stack (Fig. 13; cavity 1302 exposes a top surface of the device layer stack and sidewalls of the device sub-stacks).
Ando fails to disclose wherein the method further comprises: forming in the opening a bottom mask layer surrounding the bottom device sub-stack; and using the bottom mask layer as an etch mask for the bottom device sub-stack during the forming of the cut.
However, in analogous art, Yun discloses,
forming in the opening a bottom mask layer (Yun: mask layer 211) surrounding the bottom device sub-stack (Fig. 2E); and
using the bottom mask layer (Yun: mask layer 211) as an etch mask for the bottom device sub-stack during the forming of the cut ([0046], “[cut] 201 may be formed in the preliminary transistor stack by using the mask layer 211 as an etch mask”).
Therefore, it would have been obvious to one of ordinary skill the art prior to the effective filing date of the instant application to modify the device of Ando such that a bottom mask layer was used as an etch mask for the bottom device sub-stack while forming a cut through the device as taught by Yun. One would be motivated to do so as the use of a mask layer further prevents defects and damage to the active channel layers of the bottom device sub-stack, leading to improved device performance.
Regarding Claim 3, Ando/Yun discloses the method according to claim 2, wherein forming the bottom mask layer comprises filling the opening with a mask material (Yun: [0045], “mask layer 211 may be patterned to vertically overlap a portion (e.g., one half) of the preliminary transistor stack) and etching back the mask material to a level intermediate the at least one top channel layer and the bottom device sub-stack, and wherein the etched back mask material forms the bottom mask layer (Yun: [0046], Fig. 2F).
Regarding Claim 4, Ando/Yun discloses the method according to claim 3, further comprising removing the bottom mask layer after forming the cut and prior to forming the functional gate stack (Yun: Fig. 2F; mask layer 211 is shown to be removed from the device after it acts as the etch mask).
Regarding Claim 6, Ando discloses the method according to claim 5.
Ando fails to disclose the method further comprises forming a cut mask layer over the device structure, patterning an aperture in the cut mask layer, and sequentially transferring the aperture into the sacrificial gate structure and into the top device sub-stack by etching to form the opening and the cut.
However, in analogous art, Yun discloses a method further comprising: forming a cut mask layer (Yun: hardmask layer 215, [0049]) over the device structure (Yun: Fig. 2Y);
patterning an aperture in the cut mask layer (Yun: [0051]); and
sequentially transferring the aperture into the sacrificial gate structure and into the top device sub-stack by etching to form the opening and the cut (Yun: [0051]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of forming the device of Ando by introducing a hardmask layer and performing the associated steps as disclosed by Yun. One would be motivated to do so as the use of mask layers is known in the art to be used to protect active layers from inadvertent damage during an etchant process in order to increase device performance and stability.
Regarding Claim 8, Ando discloses the method according to claim 1.
Ando fails to disclose the method further comprising applying, via the cut, an isotropic etching process for removing portions of each of the at least one top channel layer remaining along the cut.
However, in analogous art, Yun discloses applying, via the cut, an isotropic etching process for removing portions of each of the at least one top channel layer remaining along the cut ([0046], “the upper ones of the preliminary nanosheets NS-P [NS-U] are etched to narrow the width thereof”; isotropic etching is a form of etching as called for in Yun; it can be reasonably inferred that one can of ordinary skill in the art could then narrow the width of each remaining nanosheet to zero, thereby removing all remaining portions).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method steps as disclosed by Ando such that an additional step of etching/removing portions of each of the at least one top channel layer remaining along the cut as disclosed by Yun is performed. One would be motivated to do so as narrowing the width of the top channel layers to the point of removal would reduce device weight and, therefore, make the device more efficient.
Regarding Claim 11, Ando discloses the method according to claim 1,
wherein the device layer stack is a first device layer stack (FET stack 406, Fig. 9),
wherein the sacrificial gate structure is a first sacrificial gate structure (sacrificial gate 334, Fig. 9),
wherein the device structure further comprises:
a second device layer stack (FET stack 404, Fig. 9) comprising:
a bottom device sub-stack comprising at least one bottom channel layer (lower nanosheets 308b, 312b, 316b); and
a top device sub-stack comprising at least one top channel layer (upper nanosheets 320b, 324b, 328b); and
bottom source/drain structures on opposite ends of the at least one bottom channel layer of the bottom device sub-stack of the second device layer stack (lower source and drains 502, Fig. 9),
wherein the first sacrificial gate structure or a second sacrificial gate structure parallel to the first sacrificial gate structure extends across the second device layer stack (sacrificial gate 332, Fig. 9), and
wherein the method further comprises:
forming by epitaxy top source/drain structures on opposite ends of the at least one top channel layer of the top device sub-stack of the second device layer stack (upper source and drains 602, Col. 7, lines 45-47, Fig. 9; “Specifically, an epitaxial growth process is first employed to form source and drains on opposite sides of FET stacks 402, 404, and 406”).
Ando fails to disclose that the method further comprises, subsequent to forming the cut through the top device sub-stack of the first device layer stack, forming a functional gate stack on the at least one bottom channel layer of the bottom device sub-stack and the at least one top channel layer of the top device sub-stack of the second device layer stack. Rather, Ando discloses forming the functional gate stack on the at least one bottom channel layer of the bottom device sub-stack and the at least one top channel layer of the top device sub-stack of the second device layer stack prior to forming the cut through the first device layer stack.
However, in analogous art, Yun discloses subsequent to forming the cut through the top device sub-stack of the first device layer stack, forming a functional gate stack on the at least one bottom channel layer of the bottom device layer stack (lower gate G-L, Fig. 4P) and the at least one top channel layer of the top device sub-stack of the second device layer stack (upper gate G-U, [0019], Fig. 4P; each transistor stack will be of similar design).
Since there was a design need at the time of the effective filing date of the instant application (i.e., the need to increase transistor density and reduce electrical vulnerabilities (Yun: [0003]), and there is only a finite number of times when one can form the functional gate stack in the process (i.e., either before or after the formation of the cut), and a predictable result would occur (e.g., a functioning gate), one of ordinary skill in the art could have pursued trying to form the functional gate stack prior to the formation of the cut in the first device layer stack. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to form the functional gate stack as disclosed in Ando by forming said gate stack prior to forming the cut through the top device sub-stack of the first device layer stack as disclosed in Yun.
Regarding Claim 12, Ando/Yun discloses the method according to claim 11, wherein the top source/drain structures are formed prior to forming the opening and the cut (Ando: Fig. 6, which displays a step in the method process prior to the formation of the opening and cut in which the top source/drain structures are formed).
Regarding Claim 13, Ando/Yun discloses the method of claim 11,
wherein the device structure further comprises a fin structure comprising the first device layer stack and the second device layer stack (Yun: [0028], “Though the transistors T-L, T-U are shown in FIG. 1B as nanosheet transistors, at least one of the transistors T-L, T-U may, in some embodiments, be a vertical field-effect transistor (“VFET”) or a fin field-effect transistor (“FinFET”). For example, the lower transistor T-L may be a nanosheet transistor as shown in FIG. 1B, and the upper transistor T-U may be a VFET or FinFET that may have a single channel region rather than the plurality of upper nanosheets NS-U”),
wherein the second sacrificial gate structure extends across the second device layer stack (Yun: Figs. 4A-D),
wherein one of the bottom source/drain structures is a merged epitaxial source/drain structure formed between the first and second sacrificial gate structures on the respective at least one bottom channel layer of the first and the second device layer stack (Yun: Fig. 4P, which shows the merged source/drain structure between multiple bottom/lower channel device layer stacks), and
wherein the method further comprises:
applying, via the cut, an isotropic etching process for removing portions of each of the at least one top channel layer of the first device layer sub-stack remaining along the cut (Yun: [0046], “the upper ones of the preliminary nanosheets NS-P [NS-U] are etched to narrow the width thereof”; isotropic etching is a form of etching as called for in Yun); and
subsequent to applying the isotropic etching process, forming the top source/drain structures on opposite ends of the at least one top channel layer of the top device sub-stack of the second device layer stack (Yun: upper source/drain region 150-U, Fig. 2Y; the method of a first stack is the same as the method of the second stack).
Regarding Claim 14, Ando discloses the method according to claim 1, wherein the device layer stack further comprises a dielectric separation layer intermediate the bottom and top device sub-stacks (isolation spacer 504, Fig. 13).
Ando fails to explicitly disclose wherein the etching for forming the cut through the top device sub-stack is stopped over or at the dielectric separation layer, as Ando only discloses that the etch for forming the cut goes beyond the isolation spacer but stops prior to the bottom device sub-stack.
However, in analogous art, Yun discloses wherein the etching for forming the cut through the top device sub-stack is stopped over or at the dielectric separation layer (Yun: sacrificial layer RL, [0039, 0046], Fig. 2F).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the cut as disclosed by Ando such that it stopped at or before the dielectric separation layer as disclosed by Yun. One would be motivated to do so as maintaining the dielectric separation layer between the cut upper stack and active lower stack reduces the possibility of parasitic capacitance between the inactive and active layers and can lead to increased device performance.
Regarding Claim 15, Ando/Yun discloses the method according to claim 14, wherein the separation layer is formed of a sacrificial semiconductor material (Yun: [0040], “The sacrificial layer RL may comprise a first sacrificial material that has etch selectivity with respect to a second sacrificial material of the sacrificial layers SL (and with respect to the preliminary nanosheets NS-P). For example, the sacrificial layer RL may comprise Si”), wherein the etching for forming the cut through the top device sub-stack is stopped over or at the separation layer (Yun: Fig. 2F), and wherein the method further comprises removing the separation layer by selective etching of the sacrificial semiconductor material, after forming the cut and prior to forming the functional gate stack (Yun: [0111]).
Regarding Claim 17, Ando discloses the semiconductor device according to claim 16,
wherein the opening is formed to expose a top surface of the device layer stack and sidewalls of the bottom device sub-stack and the top device sub-stack (Fig. 13; cavity 1302 exposes a top surface of the device layer stack and sidewalls of the device sub-stacks), and
Ando fails to disclose wherein the method further comprises: forming in the opening a bottom mask layer surrounding the bottom device sub-stack; and using the bottom mask layer as an etch mask for the bottom device sub-stack during the forming of the cut.
However, in analogous art, Yun discloses,
forming in the opening a bottom mask layer (Yun: mask layer 211) surrounding the bottom device sub-stack (Fig. 2E); and
using the bottom mask layer (Yun: mask layer 211) as an etch mask for the bottom device sub-stack during the forming of the cut ([0046], “[cut] 201 may be formed in the preliminary transistor stack by using the mask layer 211 as an etch mask”).
Therefore, it would have been obvious to one of ordinary skill the art prior to the effective filing date of the instant application to modify the device of Ando such that a bottom mask layer was used as an etch mask for the bottom device sub-stack while forming a cut through the device as taught by Yun. One would be motivated to do so as the use of a mask layer further prevents defects and damage to the active channel layers of the bottom device sub-stack, leading to improved device performance.
Regarding Claim 20, Ando discloses the semiconductor device according to claim 16.
Ando fails to disclose the method further comprising applying, via the cut, an isotropic etching process for removing portions of each of the at least one top channel layer remaining along the cut.
However, in analogous art, Yun discloses applying, via the cut, an isotropic etching process for removing portions of each of the at least one top channel layer remaining along the cut ([0046], “the upper ones of the preliminary nanosheets NS-P [NS-U] are etched to narrow the width thereof”; isotropic etching is a form of etching as called for in Yun; it can be reasonably inferred that one can of ordinary skill in the art could then narrow the width of each remaining nanosheet to zero, thereby removing all remaining portions).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method steps as disclosed by Ando such that an additional step of etching/removing portions of each of the at least one top channel layer remaining along the cut as disclosed by Yun is performed. One would be motivated to do so as narrowing the width of the top channel layers to the point of removal would reduce device weight and, therefore, make the device more efficient.
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner’s statement of reasons for allowance:
Regarding Claim 9, the closest prior art of record, the combination of Ando/Yun, discloses the method according to claim 8, wherein the device structure further comprises a gate spacer (Ando: sacrificial gate spacers 335, Yun: spacers 216) formed on sidewalls of the sacrificial gate structure (Ando: Fig. 13, Yun: Fig. 2L). However, the combination of Ando/Yun fails to disclose or teach that an isotropic etching process removes end portions of each of the at least one top channel layer remaining below the gate spacer after forming the cut. There is no other prior art identified that can be combined with Yun to make Claim 9 obvious considering the inherited limitations from Claims 1 and 8.
Regarding Claim 10, said claim further limits an already allowable claim; therefore, it would be allowable if rewritten as stated above.
Response to Arguments
Applicant’s arguments, see pages 15-18, filed July 20th, 2026, with respect to the rejection(s) of Claim(s) 1-20 under 35 USC § 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ando. Specifically, Ando discloses the added limitation that the cut is configured to prevent formation of an active top device during subsequent process steps. Examiner is in agreement that Yun’s claimed cut did not prevent the formation of an active top device and, therefore, a new ground of rejection was required in light of the amendments made.
Applicant’s arguments with respect to Claim 7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In the interest of compact prosecution, Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to overcome the rejection of Claims 1-8, and 11-20 before filing a written response to this Final Office Action. For example, Examiner suggests Applicant incorporate the allowable subject matter form Claims 9 and 10 into Claims 1 and 16 and therefore cancel Claims 9 and 10 to place the claims in condition for allowance. Should Applicant disagree with the above rejections/response to arguments, then Examiner suggests Applicant clarify more specifically when the cut is performed in the process to distinguish over the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The Examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights