Prosecution Insights
Last updated: August 06, 2026
Application No. 18/544,028

EPITAXIAL WAFER STRUCTURE AND FUNCTIONAL DEVICE, AND MANUFACTURING METHODS THEREOF

Non-Final OA §102§103§112
Filed
Dec 18, 2023
Priority
Aug 24, 2023 — CN 202311077989.1
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wuhan Tuopu Jingyan Semiconductor Technology Co. Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
673 granted / 935 resolved
+4.0% vs TC avg
Strong +18% interview lift
Without
With
+18.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
57 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
18.2%
-21.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 935 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 10-13 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on is acknowledge. Applicant traverses the requirement to the extent of requesting that claims in Group II that correspond to allowable Group I claims be reinstated for allowance. There are no allowable claims. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “the plurality of function bonding layers” lacks antecedent basis. As such it is unclear and indefinite. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. 20220013502 (Lee). PNG media_image1.png 451 532 media_image1.png Greyscale PNG media_image2.png 588 479 media_image2.png Greyscale Regarding claim 1, figs. 3-4 of Lee discloses an epitaxial wafer structure 10C, configured to be bonded to a driver substrate 20C provided with a plurality of driver units comprising a plurality of non-defective driver units 26s and a plurality of defective driver units (dummy pads on 20C), comprising: a carrier substrate 10W; a plurality of functional units 16s disposed on the carrier substrate; and a plurality of placeholder units (dummy pads on 10C in DPR region) disposed on the carrier substrate; wherein each of the plurality of functional units 16s on the carrier substrate is corresponding in position to one of the plurality of non-defective driver units 26 on the driver substrate; and each of the plurality of placeholder units (dummy pads on 10C in DPR region) on the carrier substrate 10W is corresponding in position to one of the plurality of defective driver units (dummy pads on 20C) on the driver substrate. Regarding claim 3, fig. 4 of Lee discloses wherein surfaces of the placeholder units away from the carrier substrate are flush with surfaces of the functional units away from the carrier substrate. Regarding claim 4, fig. 4 of Lee discloses further comprising a plurality of first bonding layers 10MS/10UI disposed between the plurality of functional units and the carrier substrate, respectively, wherein the plurality of functional units are bonded to the carrier substrate via the plurality of first bonding layers. Regarding claim 5. The epitaxial wafer structure of claim 4, further comprising a third bonding layer (layer below 10MS and 10W) covering the carrier substrate and disposed between the plurality of first bonding layers and the carrier substrate, wherein the plurality of function bonding layers 10TRs are bonded to the third bonding layer. PNG media_image3.png 670 517 media_image3.png Greyscale Regarding claims 1 and 7, figs. 3-4 (as labeled by examiner above) of Lee discloses an epitaxial wafer structure 10C, configured to be bonded to a driver substrate 20C provided with a plurality of driver units comprising a plurality of non-defective driver units 26s and a plurality of defective driver units (dummy pads on 20C), comprising: a carrier substrate 10W; a plurality of functional units (solid line units for non dummy region) disposed on the carrier substrate; and a plurality of placeholder units (dotted line units for dummy region) disposed on the carrier substrate; wherein each of the plurality of functional units on the carrier substrate is corresponding in position to one of the plurality of non-defective driver units 26 on the driver substrate; and each of the plurality of placeholder units on the carrier substrate 10W is corresponding in position to one of the plurality of defective driver units on the driver substrate; wherein the plurality of placeholder units are made of a semiconductor material (par [0027]), the epitaxial wafer structure further comprises a plurality of second bonding layers (source and drain layers and channel layer below transistors which bonds transistor to substrate) disposed between the plurality of placeholder units and the carrier substrate, respectively, and the plurality of placeholder units are bonded to the carrier substrate via the plurality of second bonding layers. Claims 1-2 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youn et al. 20190189969. PNG media_image4.png 459 747 media_image4.png Greyscale Regarding claim 1, fig. 9 of Youn discloses an epitaxial wafer structure, configured to be bonded to a driver substrate 100/200 provided with a plurality of driver units (400s and 330 are units on driver substrate) comprising a plurality of non-defective driver units 300s and a plurality of defective driver units 400s (this is defective compare to 300 as it is not conductive), comprising: a carrier substrate 900; a plurality of functional units (RGB 510/520/530) disposed on the carrier substrate; and a plurality of placeholder units Ds(550s) disposed on the carrier substrate; wherein each of the plurality of functional units 510/520/530 on the carrier substrate is corresponding in position to one of the plurality of non-defective driver units (to 300 for each of 510/520/530) on the driver substrate; and each of the plurality of placeholder units 550 on the carrier substrate is corresponding in position to one of the plurality of defective driver units 400 on the driver substrate. Regarding claim 2, fig. 9 of Youn discloses wherein each of the plurality of functional units comprises a micro light emitting diode. Regarding claim 8, fig. 9 of Youn discloses further comprising a dielectric layer 400 disposed in a space between any adjacent two of the plurality of functional units, between any adjacent two of the plurality of placeholder units, or between one of the plurality of functional units and one of the plurality of placeholder units adjacent to each other. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee. Regarding claim 6, par [0057] of Lee discloses wherein a material of the plurality of first bonding layers is selected from a group consisting of silicon oxide. Furthermore, it would have been obvious to form a structure wherein a material of the third bonding layer is selected from a group consisting of silicon oxide, silicon nitride, epoxy resin, polyimide, indium tin oxide, metal, and any combination thereof as these are well known insulating material for applicant purpose of ease. Regarding claim 14, figs. 3-4 of Lee discloses a functional device, comprising: a driver substrate 20C; a plurality of driver units disposed on the driver substrate and comprising a plurality of non-defective driver units 26 and at a plurality of defective driver units (dummy pads of DPRs); a plurality of functional units 16 (on 10C) located opposite to and electrically connected to the plurality of non-defective driver units, respectively; and a plurality of placeholder units (dummy pads on 10C) located opposite to the plurality of defective driver units, respectively; Lee does not discloses of wherein the plurality of functional units and the plurality of placeholder units are transferred from an epitaxial wafer structure to the driver substrate, the epitaxial wafer structure comprising a carrier substrate on which the plurality of functional units and the plurality of placeholder units are arranged corresponding to positions of the plurality of non-defective driver units and the plurality of defective driver units, respectively, and wherein the carrier substrate has been removed from the functional device. Note this is product by process step. However, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). As such, the patentability of the product does not depend on the process steps. Therefore, the structure Lee discloses the structure regardless of the process of making such as “wherein the plurality of functional units and the plurality of placeholder units are transferred from an epitaxial wafer structure to the driver substrate, the epitaxial wafer structure comprising a carrier substrate on which the plurality of functional units and the plurality of placeholder units are arranged corresponding to positions of the plurality of non-defective driver units and the plurality of defective driver units, respectively, and wherein the carrier substrate has been removed from the functional device” . Regarding claim 15, fig. 4 of Lee discloses further comprising: a plurality of sixth bonding layers (28A/B/18A/B20MS/10MS) disposed between the plurality of functional units and the plurality of non-defective driver units, respectively; wherein the plurality of functional units are bonded to the plurality of non-defective driver units via the plurality of sixth bonding layers, respectively. Regarding claim 16, fig. 4 of Lee discloses wherein a material of the plurality of sixth bonding layers comprises metal. Regarding claim 17, fig. 4 of Lee discloses further comprising: a plurality of electrode layers disposed between the plurality of functional units and the plurality of non-defective driver units, respectively. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Youn. Regarding claim 9, Youn discloses wherein the plurality of placeholder units are made of a dielectric material (as it is has some type of dielectric constant). Youn does not disclose the plurality of placeholder units are made of a dielectric material same as that of the dielectric layer. However, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). As such, the patentability of the product does not depend on the process steps. Therefore, the structure Youn discloses the structure regardless of the process of making. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 18, 2023
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.5%)
3y 3m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 935 resolved cases by this examiner. Grant probability derived from career allowance rate.

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