Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 11, lines 7-22, filed 06/29/2026, with respect to the rejection of claim 1 under 35 USC § 103 have been fully considered. Based on applicant’s amendments, a new ground(s) of rejection is made in view of Ramappa (US 20100112788 A1), as discussed below.
Applicant's arguments with respect to claim 9 have been fully considered but they are not persuasive. Applicant argues (see page 12) that claim 9 recites analogous limitations to claim 1, and has been amended in an analogous manner, and therefore render the rejection of claim 9 moot. Examiner responds that claim 9 lacks the limitation “the activation annealing of dopants being provided so as not to recrystallize, and keep amorphous, said amorphous semiconductor regions”. Therefore, the claim is still rejected over the combination of Yu and Mazara, as discussed below.
Specification
The objections regarding the abstract and the specification have been withdrawn in light of the Applicant’s amendments
Claim Objections
The objections from the previous office action regarding claims 2, 4, 5, 12, and 13 have been withdrawn in light of the Applicant’s amendments.
Claims 1 and 9 objected to because of the following informalities:
The claims recite “the method further comprises […] at least one activation annealing of dopants” (lines 18-21 of claim 1 and lines 18-20 of claim 9). This phrasing seems improper, and it is suggested to change it to “the method further comprises […] performing at least one activation annealing of dopants”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Yu figures 4, 7, 13, and 14 above. Maszara figure 7 below.
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Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 6893930 B1, hereinafter referred to as "Yu"), in view of Maszara (US 2011/0062443 A1 hereinafter, referred to as "Maszara").
Regarding claim 9, Yu discloses a method for manufacturing at least one transistor structure, the method comprising: forming on a substrate (204 in Yu figure 4): a gate block on the surface semiconductor layer (214 in Yu figure 4) and insulating spacers on either side of said gate block (220 in Yu figure 7), amorphizing semiconductor regions of said surface semiconductor layer situated on either side of the gate block to form amorphous semiconductor regions (Yu Figure 13, column 7, lines 7-12), while retaining at least one crystalline semiconductor zone of the surface semiconductor layer below the gate block (Yu Figure 13, area between 252/216 and 224/218), forming, metal-semiconductor alloy regions in the amorphous semiconductor regions of the surface semiconductor layer (242 and 244 in Yu figure 14; column 7, lines 33-42), wherein the method further comprises, prior to the amorphizing or concurrently with the amorphizing of said semiconductor regions: doping portions of the surface semiconductor layer on either side of said crystalline zone (Figure 4; column 4, lines 35-42), and the method further comprises, after doping said portions of the surface semiconductor layer and forming said metal-semiconductor alloy regions, at least one activation annealing of dopants (column 7, lines 40-51).
Yu does not disclose that the substrate has an insulating layer and a surface semiconductor layer resting on the insulating layer.
Maszara teaches a substrate having an insulating layer and a surface semiconductor layer resting on the insulating layer (42 in Maszara figure 7; Insulating layer is 46, and semiconductor layer is 44). Maszara also teaches that it is increasingly common to produce metal oxide semiconductors on these Silicon-on-Insulator (SOI) substrates, and furthermore teaches that, compared to MOS transistors on bulk wafers, transistors on SOI substrates achieve lower junction capacitances and higher operational speeds (paragraphs 0002 and 0003).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method taught by Yu with a SOI substrate as disclosed by Maszara to lower the junction capacitance and increase the operational speeds of the transistor formed.
Regarding claim 10, Yu in view of Maszara teaches all of the limitations of claim 9. Yu further discloses that the amorphizing of said semiconductor regions is performed by ion implantation so as to concurrently dope said semiconductor regions of the surface semiconductor layer (Yu column 7, lines 3-7).
Regarding claim 11, Yu in view of Maszara teaches all of the limitations of claim 9. Yu further discloses that prior to the amorphizing of said semiconductor regions, implantation is performed so as to dope extension zones of the surface semiconductor layer (figure 4 in Yu; column 4, lines 35-39), the insulating spacers being arranged opposite said extension zones (220 in Yu figure 7).
Regarding claim 12, Yu in view of Maszara teaches all of the limitations of claim 11. Yu further discloses that said extension zones are doped by implantation by means of a beam parallel to a normal (n) to a main plane of the substrate (figure, 4 in Yu; column 4, lines 35-39. Implantation is depicted as parallel to a normal to a main plane of the substrate, as is common in the art) prior to the forming of the insulating spacers on either side of said gate block (Yu column 5, lines 45-48), and the amorphizing of the semiconductor regions is performed after forming said insulating spacers (Yu figure 13; column 7, lines 7-12).
Regarding claim 13, Yu in view of Maszara teaches all of the limitations of claim 11, wherein the extension zones are doped by implantation of antimony.
Yu does not teach that said extension zones are doped after the forming of said insulating spacers on either side of said gate block, by implantation with a beam inclined relative to a normal to a main plane of the substrate.
Maszara teaches implantation with a beam inclined relative to a normal to a main plane of the substrate after the forming of the insulating spacers (Maszara paragraph 0027 “ion bombardment can be performed at an angle”. Figure 7, sidewall spacers 74, 76 are already formed). Maszara also teaches that this is done to “to adjust the lateral position of the amorphized/un-amorphized silicon juncture as desired”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the implantation doping of Yu to be an angled beam as in Maszara to adjust the lateral position of the doped/undoped silicon juncture instead of the amorphized/un-amorphized silicon juncture and thus dope the area underneath the insulating spacers.
Regarding claim 14, Yu in view of Maszara teaches all of the limitations of claim 9, wherein the amorphizing of said semiconductor regions comprises implantation.
Yu does not teach that the implantation is with a beam inclined relative to a normal to a main plane of the substrate.
Maszara teaches a step involving amorphizing semiconductor regions comprising implantation with a beam inclined relative to a normal to a main plane of the substrate (Maszara paragraph 0027 “ion bombardment can be performed at an angle”). Maszara also teaches that this is done to “to adjust the lateral position of the amorphized/un-amorphized silicon juncture as desired”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yu with the angled bombardment of Maszara in order to adjust the lateral position of the amorphized/un-amorphized silicon juncture.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Maszara as applied to claim 9 above, and further in view of Reboh (US 20210305097 A1), hereinafter referred to as "Reboh".
Regarding claim 15, Yu in view of Maszara teaches all of the limitations of claim 9.
Neither Yu nor Maszara teach that the substrate is provided with one or more components of a first level of components formed in an underlying semiconductor layer.
Reboh discloses a substrate provided with one or more components of a first level of components formed in an underlying semiconductor layer (paragraph 0002, “Such a 3D device thus generally includes a lower level provided with a first semiconductor layer from which transistors are formed and at least one upper level provided with at least one second semiconductor layer from which transistors are formed”.) Reboh also discloses that this is a solution to the problem of increasing the density of transistors in integrated circuits.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the method of Yu and Maszara on the substrate of Reboh in order to increase the density of the produced transistors.
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Komatsu figures 4G and 4H.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Maszara as applied to claim 9 above, and further in view of Komatsu (US 6773970 B2), hereinafter referred to as "Komatsu".
Regarding claim 16, Yu in view of Maszara teaches all of the limitations of claim 9.
Neither Yu nor Maszara disclose forming at least one insulating layer on the metal-semiconductor alloy regions and the gate, making at least one opening exposing at least one given region among said metal-semiconductor alloy regions, or forming a conductive pad in contact with said given region.
Komatsu teaches forming at least one insulating layer on the metal-semiconductor alloy regions and the gate block (14 in Komatsu figure 4H. This is on part 13, labeled in figure 4G, which is a metal silicide layer), making at least one opening exposing at least one given region among said metal-semiconductor alloy regions (15 in Komatsu figure 4H), and forming a conductive pad in contact with said given region (16 and 17 in Komatsu figure 4H). Komatsu also teaches that the interconnect 17 connects the plug 16 electrically, and that these steps finish forming the nMOS (column 6, 38-40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the steps of Komatsu to the method of Yu and Maszara to finish the MOS and electrically connect it to higher components, allowing for both electrical access to the transistor and insulation between other components.
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Ramappa figure 3A
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Maszara and Ramappa (US 20100112788 A1, hereinafter referred to as “Ramappa”).
Regarding claim 1, Yu discloses a method for manufacturing at least one transistor structure, comprising
forming, on a substrate (204 in Yu figure 4), a gate block on the surface semiconductor layer (214 in Yu figure 4) and insulating spacers on either side of said gate block (220 in Yu figure 7), amorphizing semiconductor regions of said surface semiconductor layer (242 and 244 in Yu figure 14; column 7, lines 33-42) to form amorphous semiconductor regions situated on either side of the gate block, while retaining at least one crystalline semiconductor zone of the surface semiconductor layer below the gate block (Yu Figure 13, area between 252/216 and 224/218), and forming metal-semiconductor alloy regions in the amorphous semiconductor regions of the surface semiconductor layer (242 and 244 in Yu figure 14; column 7, lines 33-42), wherein the method further comprises, prior to the amorphizing or concurrently with the amorphizing said semiconductor regions, doping portions of the surface semiconductor layer on either side of said crystalline zone (Figure 4; column 4, lines 35-42), and the method further comprises, prior to the forming of the metal-semiconductor alloy regions and after doping said portions of the surface semiconductor layer and the amorphizing of said semiconductor regions, at least one activation annealing of dopants column 7, lines 20-23).
Yu does not disclose that the substrate has an insulating layer and a surface semiconductor layer resting on the insulating layer, nor that the activation annealing is provided to not recrystallize the amorphous semiconductor regions.
Maszara teaches a substrate having an insulating layer and a surface semiconductor layer resting on the insulator (42 in Maszara figure 7; Insulating layer is 46, and semiconductor layer is 44). Maszara also teaches that it is increasingly common to produce metal oxide semiconductors on these Silicon-on-Insulator (SOI) substrates, and furthermore teaches that, compared to MOS transistors on bulk wafers, transistors on SOI substrates achieve lower junction capacitances and higher operational speeds (paragraphs 0002 and 0003).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method taught by Yu with a SOI substrate as disclosed by Maszara to lower the junction capacitance and increase the operational speeds of the transistor formed.
Ramappa teaches at least one activation annealing of dopants (301 in Ramappa figure 3A; see Ramappa paragraph 0022), the activation annealing of dopants being provided so as not to recrystallize, and keep amorphous, said amorphous semiconductor regions (it is a RTA, spike, flash or laser anneal, [paragraph 0022] and it remains amorphous through to the silicidation [paragraph 0029]). Ramappa also teaches that the crystal lattice being amorphous helps improve uniformity of the silicidation and may reduce metal diffusion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an activation annealing step which does not recrystallize the lattice, as in Ramappa, in order to help improve uniformity of the silicidation and reduce metal diffusion.
Regarding claim 2, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 1. Yu further discloses that the amorphizing of said semiconductor regions is performed by ion implantation so as to concurrently dope said semiconductor regions of the surface semiconductor layer (Yu column 7, lines 3-7).
Regarding claim 3, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 1. Yu further discloses that prior to the amorphizing of said semiconductor regions, implantation is performed so as to dope extension zones of the surface semiconductor layer (figure 4 in Yu; column 4, lines 35-39), the insulating spacers being arranged opposite said extension zones (220 in Yu figure 7).
Regarding claim 4, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 3. Yu further discloses that said extension zones are doped by implantation by means of a beam parallel to a normal (n) to a main plane of the substrate (figure, 4 in Yu; column 4, lines 35-39. Implantation is depicted as parallel to a normal to a main plane of the substrate, as is common in the art) and prior to the forming of the insulating spacers on either side of said gate block (Yu column 5, lines 45-48), and the amorphizing of the semiconductor regions is performed after the formation of said insulating spacers (Yu figure 13; column 7, lines 7-12).
Regarding claim 5, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 3, wherein the extension zones are doped by implantation of antimony.
Yu does not teach that said extension zones are doped after the forming of said insulating spacers on either side of said gate block, by implantation with a beam inclined relative to a normal to a main plane of the substrate.
Maszara teaches implantation with a beam inclined relative to a normal to a main plane of the substrate after the formation of the insulating spacers (Maszara paragraph 0027 “ion bombardment can be performed at an angle”. Figure 7, sidewall spacers 74, 76 are already formed). Maszara also teaches that this is done to “to adjust the lateral position of the amorphized/un-amorphized silicon juncture as desired”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the implantation doping of Yu to be an angled beam as in Maszara to adjust the lateral position of the doped/undoped silicon juncture instead of the amorphized/un-amorphized silicon juncture and thus dope the area underneath the insulating spacers.
Regarding claim 6, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 1, wherein the step involving amorphizing said semiconductor regions comprises implantation.
Yu does not teach that the implantation is with a beam inclined relative to a normal to a main plane of the substrate.
Maszara teaches a step involving amorphizing semiconductor regions comprising implantation with a beam inclined relative to a normal to a main plane of the substrate (Maszara paragraph 0027 “ion bombardment can be performed at an angle”). Maszara also teaches that this is done to “to adjust the lateral position of the amorphized/un-amorphized silicon juncture as desired”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yu with the angled bombardment of Maszara in order to adjust the lateral position of the amorphized/un-amorphized silicon juncture.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Maszara and Ramappa as applied to claim 1 above, and further in view of Reboh.
Regarding claim 7, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 1.
Neither Yu nor Maszara teach that the substrate is provided with one or more components of a first level of components formed in an underlying semiconductor layer.
Reboh discloses a substrate provided with one or more components of a first level of components formed in an underlying semiconductor layer (paragraph 0002, “Such a 3D device thus generally includes a lower level provided with a first semiconductor layer from which transistors are formed and at least one upper level provided with at least one second semiconductor layer from which transistors are formed”.) Reboh also discloses that this is a solution to the problem of increasing the density of transistors in integrated circuits.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform the method of Yu and Maszara on the substrate of Reboh in order to increase the density of the produced transistors.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Maszara and Ramappa as applied to claim1 above, and further in view of Komatsu.
Regarding claim 8, Yu in view of Maszara and Ramappa teaches all of the limitations of claim 1.
Neither Yu nor Maszara disclose forming at least one insulating layer on the metal-semiconductor alloy regions and the gate block, making at least one opening exposing at least one given region among said metal-semiconductor alloy regions, or forming a conductive pad in contact with said given region.
Komatsu teaches forming at least one insulating layer on the metal-semiconductor alloy regions and the gate block (14 in Komatsu figure 4H. This is on part 13, labeled in figure 4G, which is a metal silicide layer), making at least one opening exposing at least one given region among said metal-semiconductor alloy regions (15 in Komatsu figure 4H), and forming a conductive pad in contact with said given region (16 and 17 in Komatsu figure 4H). Komatsu also teaches that the interconnect 17 connects the plug 16 electrically, and that these steps finish forming the nMOS (column 6, 38-40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the steps of Komatsu to the method of Yu and Maszara to finish the MOS and electrically connect it to higher components, allowing for both electrical access to the transistor and insulation between other components.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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