DETAILED ACTION
This action is in response to argument and amendments filed for Application 18/544081 on March 22, 2024, in which Claims 1-17 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-17 are pending, of which Claims 1, 4, 7-9, 11, 13-15 and 17 are rejected under 112b. Claims 2, 3, 5, 6, 10, 12 and 16 are objected to.
Allowable Subject Matter
Claims 2, 3, 5, 6, 10, 12 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 7-9, 11, 13-15 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the same plurality of word lines" in Line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the pages" in Line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the number of rows" in Line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the same coding equation" in Line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the memory strings" in Line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the word lines" in Line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the memory devices" in Line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the memory device" in Line 4 and 12. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the errors" in Line 23. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the page rows" in Line 2 and 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the error data" in Line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the same coding equation" in Lines 10-11. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the error" in Line 15. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the page rows" in Line 2 and 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the same coding equation" in Line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the error data" in Line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the errors" in Line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the process" in Line 4. There is insufficient antecedent basis for this limitation in the claim.
Reasons for Indicating Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: Upon searching a variety of databases, the examiner considers “each of the plurality of groups of check data corresponds to a plurality of page rows in each of designated word lines, the designated word lines comprising multiple word lines without an interval or with a fixed interval; and each group of check data is obtained from data stored in corresponding page rows and a plurality of different coding equations” in Claims 1, 9 and 15; in conjunction with all other limitations of the dependent and independent claims are not taught or suggested by the prior art of record (PTO-892).
Prior Art Made of Record
From a search of the prior art, one reference was found and considered by the Examiner to be the most-related prior art with regards to the claimed invention of the instant application:
Hirano et al. (U.S. Patent Application Publication No. 2017/0329556 A1), hereinafter “Hirano”. Hirano is cited on PTO-892 filed 3/22/2026.
Hirano: Paragraph 10 teaches in a method of reading a nonvolatile memory device including a plurality of pages coupled to a plurality of word lines and a plurality of bit lines, where each of the plurality of pages includes a data region storing a data and a flag region storing a flag corresponding to information of the data region, a first read voltage is applied to a selected word line among the plurality of word lines to generate first sensing data and a first sensing flag, which correspond to the data and the flag, respectively, stored in a selected page coupled to the selected word line, by sensing the plurality of bit lines, a second read voltage is applied to the selected word line to generate a second sensing data and a second sensing flag, which correspond to the data and the flag, respectively, stored in the selected page, by sensing the plurality of bit lines, determination data is generated by performing a logical operation on the first sensing data and the second sensing data, a count value is generated by counting a number of bits having a first logic level included in the determination data, a read flag is generated by performing an error check and correction operation on one of the first sensing flag and the second sensing flag, a shift voltage is determined based on the count value and the read flag, and a third read voltage, which is determined by shifting the first read voltage by the shift voltage, is applied to the selected word line to generate a read data, which corresponds to the data stored in the selected page, by sensing the plurality of bit lines.
Although conceptually similar to the claimed invention of the instant application, Hirano does not teach each of the plurality of groups of check data corresponds to a plurality of page rows in each of designated word lines, the designated word lines comprising multiple word lines without an interval or with a fixed interval; and each group of check data is obtained from data stored in corresponding page rows and a plurality of different coding equations.
Additional Prior Art Made of Record
Voicila et al. (U.S. Patent Publication No. 8,627,153) teaches the variable q may be equal to 2.sup.p, with p strictly greater than 1, and each order less than q is also an integer power of 2. The definition of the code characteristics may comprise forming a first matrix possessing N-K groups of p rows respectively associated with the N-K parity check equations, and N groups of p columns respectively associated with the N symbols. Each group of p rows may comprise bit blocks of p rows and of p columns forming respectively binary matrix images of the nonzero coefficients of the parity check equation associated with the d group of p rows considered. Each of these blocks, associated with a symbol, may be subdivided into j bit sub-blocks of p rows and of p.sub.i columns respectively situated at different locations on the group of p rows. For the values of the numbers j and p.sub.i, i varies from 1 to j. The subdivision may also be the positions of the various locations of the sub-blocks forming a block associated with an encoded symbol may be representative of part of the subdivision scheme associated with the encoded symbol. The string of encoded symbols may be obtained on the basis of the first matrix and of the string of initial symbols.
Jeon et al. (U.S. Patent Application Publication No. 2014/0281750 A1) teaches the data storage device includes a memory die that includes the non-volatile memory and that is coupled to a controller die that includes the controller. The non-volatile memory may be a flash memory, such as a NAND flash memory. The non-volatile memory includes multiple groups of storage elements, such as a first group, a second group, a third group, up to an N-1.sup.st group and an N-th group. For example, each group may be an error correction coding (ECC) page, a word line, an erase block, or another group of storage elements of a multi-level cell (MLC) flash memory.
Sharon et al. (U.S. Patent Application Publication No. 2014/0245098 A1) teaches the joint parity (e.g., the combined parity bits) increases the robustness of stored data at a MLC word line that may have unequal error rates over the logical pages of the MLC word line and transforms the plurality of individual, shorter codewords (e.g., codewords) into one longer codeword that may span over multiple (or all) logical pages of a single word line. The longer combined codeword using the second ECC scheme can have a reduced error floor and an improved error correction capability as compared to the shorter codewords using the first ECC scheme.
Otsuka et al. (U.S. Patent Publication No. 8,397,127 ) teaches a semiconductor recording device according to an aspect of the present invention further include a plurality of word lines through which a plurality of memory cells included in the at least one nonvolatile memory are selected or deselected, that each of the plurality of word lines be connected to a corresponding one of the plurality of pages, and that the control unit control the assignment of the symbol of the ECC code such that the number of symbols of the ECC code is smallest, the symbols being assigned to the pages having a same word line number in the common group.
Lien et al. (U.S. Patent Application Publication No. 2023/0066972) teaches the memory device includes a plurality of dies, a plurality of planes, a plurality of strings, and a plurality of word lines. For each combination of die, plane, and word line, the memory cells coupled with at least half of the strings are of the first set of memory cells that are programmed using the first programming operation that includes the single programming pulse and no verify pulse.
Wang et al. (U.S. Patent Application Publication No. 2012/0260125) teaches data in the disk array is arranged according to a form of a matrix M of (m+q).times.p, where m is a prime number smaller than or equal to p-q; in the matrix M, a 0.sup.th row is virtual data blocks being virtual and having values being 0, a 1.sup.st row to an (m-1).sup.th row are data blocks, an m.sup.th row to an (m+q-1).sup.th row are a check area; where for each data block in a check group in which a check block C.sub.m-1+l,n in the check area is located, a row number is m-kl, a column number is n+k, a span of k is from l to m-1+l, where l is a row number of the check block in the check area, 1.ltoreq.l.ltoreq.q, n is a column number corresponding to the check block, 0.ltoreq.n.ltoreq.p-1; data in the check block is an exclusive-or (XOR) value of data of all data blocks in the check group to which the check block belongs.
Hsu et al. (U.S. Patent Application Publication No. 2022/03990720) teaches one or more control circuits configured to connect to a plurality of non-volatile memory cells arranged along word lines. The one or more control circuits are configured to receive a plurality of encoded portions of data to be programmed in non-volatile memory cells of a target word line, each encoded portion of data encoded according to an Error Correction Code (ECC) encoding scheme, and arrange the plurality of encoded portions of data in a plurality of rows of data latches corresponding to a plurality of logical pages such that each encoded portion of data is distributed across two or more rows of data latches. The one or more control circuits are also configured to program the distributed encoded portions of data from the plurality of rows of data latches into non-volatile memory cells along a target word line.
Conclusion
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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