DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Jenner, JR. (US 2007/0285040 and Jenner hereinafter).
Regarding claim 1, Jenner discloses an integrate-and-fire neuron circuit [10, fig. 1] implementing an integrate-and-fire operation, comprising: a first NPN device [Q3, par. 0010 and 0042]; a second NPN device connected in parallel to the first NPN device [Q1]; a transistor [Q2] whose one end is connected to a cathode node of the second NPN device and other end is grounded [46]; a first capacitor [C4] connected in parallel to the first NPN device and the second NPN device; and a second capacitor [C2] connected in parallel to the cathode node of the second NPN device together with the transistor. Jenner does not explicitly disclose MOS transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace the transistor Q2 of Jenner with metal-oxide-semiconductor field effect transistor [MOS transistor] because such a modification would have been merely a replacement with a well-known, art-recognized functionally equivalent transistor device.
Regarding claim 2, Jenner discloses wherein an anode terminal of the first NPN device [Q3] is connected in parallel to the first capacitor [C4] and an anode terminal of the second NPN device, and a cathode end of the first NPN device [Q3] is connected to a ground, and the anode terminal of the second NPN device [Q1] is connected in parallel to the first capacitor and the anode terminal of the first NPN device, and a cathode end of the second NPN device is connected in parallel to the MOS transistor and the second capacitor.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 4-5 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Jenner, JR.
Regarding claim 4, Jenner discloses an integrate-and-fire neuron circuit [10, fig. 1] implementing an integrate-and-fire operation, comprising: a first NPN device [Q2, par. 0010 and 0042]; a second NPN device [Q1] connected in parallel to the first NPN device; a capacitor [C2] connected in parallel to the first NPN device and the second NPN device; and an output resistor [R6] connected in series to the cathode node of the second NPN device.
Regarding claim 5, Jenner discloses wherein an anode terminal of the first NPN device is connected in parallel to the capacitor [C2] and an anode terminal of the second NPN device, and a cathode end of the first NPN device is connected to a ground [46], and the anode terminal of the second NPN device is connected in parallel to the capacitor and the anode terminal of the first NPN device, and a cathode end of the second NPN device is connected in series to the output resistor.
Allowable Subject Matter
Claims 3 and 6-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 3 and 6, Jenner does not explicitly disclose, wherein the first NPN device and the second NPN device include: a first N-type semiconductor; a P-type semiconductor whose one end is heterogeneously bonded to one end of the first N-type semiconductor; a second N-type semiconductor whose one end is heterogeneously bonded to the other end of the P-type semiconductor; a control gate formed on top of the P-type semiconductor; an anode contacting the first N-type semiconductor through an ohmic junction; a cathode contacting the second N-type semiconductor through the ohmic junction, and the first N-type semiconductor and the second N-type semiconductor have a relatively higher concentration than the P-type semiconductor, and the P-type semiconductor has a smaller band gap than the first N-type semiconductor and the second N-type semiconductor.
Conclusion
Other prior art references such as Kim et al. (US 20220006448 A1) teach features similar to the claimed invention, but do not teach the claimed invention as a whole.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
